DCGPU HSIO Validation Engineering Lead

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As an HSIO Technical Lead, you will provide deep technical expertise and leadership in the validation of high-speed I/O subsystems—including PCIe, xGMI, UAlink, IFoE, and UCIe—on AMD platforms. You will work cross-functionally with design, architecture, signal integrity, package/board, firmware/software, quality, and system/platform teams to develop comprehensive validation strategies, execute detailed test plans, debug electrical and protocol issues, and continuously improve validation coverage and methodology. Your responsibilities include margining and PHY analysis to characterize and optimize interface robustness, as well as enabling and qualifying advanced interface features. THE PERSON: This role is ideal for an engineer who enjoys deep technical debugging, lab-based validation, high-speed interfaces, and solving difficult cross-functional problems. The most successful candidates combine strong HSIO fundamentals, disciplined execution, and the ability to translate ambiguous failures into structured technical actions. KEY RESPONSIBILITIES: • Define and execute comprehensive validation strategies for PCIe, xGMI, UAlink, IFoE, and UCIe interfaces, integrating both electrical and functional aspects. • Develop and implement test plans covering signal integrity, protocol compliance, margining, PHY analysis, feature enablement, and interoperability. • Perform margining tests (voltage, timing, stress) and PHY layer analysis to optimize interface robustness and performance. • Validate and enable advanced interface features (link training, equalization, power management, security, bandwidth scaling), ensuring seamless operation and integration. • Design and implement test cases to verify functionality, performance, and reliability under a variety of scenarios and workloads. • Identify, debug, and resolve functional issues, collaborating with cross-functional teams to drive root-cause analysis and corrective actions. • Drive automation and regression testing to ensure scalability, repeatability, and coverage across all HSIO domains. • Work closely with peers across functional validation, E2E validation, quality, and sustaining teams to ensure end-to-end product success. • Collaborate effectively with engineering teams across different geographic locations, ensuring alignment on validation goals, sharing knowledge, and coordinating activities to meet project milestones. • Participate in regular meetings and communications with global teams, adapting to time zone differences and leveraging remote collaboration tools. Mentorship & Collaboration • Mentor and guide junior engineers, fostering a culture of technical excellence and continuous improvement. • Provide technical guidance and training on HSIO validation best practices, margining, PHY analysis, and feature enablement. • Communicate validation results, risks, and recommendations to stakeholders and management. Documentation & Process Improvement • Author and maintain detailed documentation for validation procedures, test results, margining reports, PHY analysis findings, and lessons learned across all HSIO domains. • Identify and implement process improvements to enhance validation efficiency and coverage. Preferred Qualifications • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. • Demonstrated expertise in high-speed signaling, protocol standards (PCIe, xGMI, UAlink, IFoE, UCIe), margining, PHY analysis, and advanced validation methodologies. • Strong hands-on experience with lab equipment, test automation, and debugging complex issues. • Excellent communication, leadership, and problem-solving skills. LOCATION: Penang, Malaysia #LI-SJ1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. THE ROLE: As an HSIO Technical Lead, you will provide deep technical expertise and leadership in the validation of high-speed I/O subsystems—including PCIe, xGMI, UAlink, IFoE, and UCIe—on AMD platforms. You will work cross-functionally with design, architecture, signal integrity, package/board, firmware/software, quality, and system/platform teams to develop comprehensive validation strategies, execute detailed test plans, debug electrical and protocol issues, and continuously improve validation coverage and methodology. Your responsibilities include margining and PHY analysis to characterize and optimize interface robustness, as well as enabling and qualifying advanced interface features. THE PERSON: This role is ideal for an engineer who enjoys deep technical debugging, lab-based validation, high-speed interfaces, and solving difficult cross-functional problems. The most successful candidates combine strong HSIO fundamentals, disciplined execution, and the ability to translate ambiguous failures into structured technical actions. KEY RESPONSIBILITIES: • Define and execute comprehensive validation strategies for PCIe, xGMI, UAlink, IFoE, and UCIe interfaces, integrating both electrical and functional aspects. • Develop and implement test plans covering signal integrity, protocol compliance, margining, PHY analysis, feature enablement, and interoperability. • Perform margining tests (voltage, timing, stress) and PHY layer analysis to optimize interface robustness and performance. • Validate and enable advanced interface features (link training, equalization, power management, security, bandwidth scaling), ensuring seamless operation and integration. • Design and implement test cases to verify functionality, performance, and reliability under a variety of scenarios and workloads. • Identify, debug, and resolve functional issues, collaborating with cross-functional teams to drive root-cause analysis and corrective actions. • Drive automation and regression testing to ensure scalability, repeatability, and coverage across all HSIO domains. • Work closely with peers across functional validation, E2E validation, quality, and sustaining teams to ensure end-to-end product success. • Collaborate effectively with engineering teams across different geographic locations, ensuring alignment on validation goals, sharing knowledge, and coordinating activities to meet project milestones. • Participate in regular meetings and communications with global teams, adapting to time zone differences and leveraging remote collaboration tools. Mentorship & Collaboration • Mentor and guide junior engineers, fostering a culture of technical excellence and continuous improvement. • Provide technical guidance and training on HSIO validation best practices, margining, PHY analysis, and feature enablement. • Communicate validation results, risks, and recommendations to stakeholders and management. Documentation & Process Improvement • Author and maintain detailed documentation for validation procedures, test results, margining reports, PHY analysis findings, and lessons learned across all HSIO domains. • Identify and implement process improvements to enhance validation efficiency and coverage. Preferred Qualifications • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. • Demonstrated expertise in high-speed signaling, protocol standards (PCIe, xGMI, UAlink, IFoE, UCIe), margining, PHY analysis, and advanced validation methodologies. • Strong hands-on experience with lab equipment, test automation, and debugging complex issues. • Excellent communication, leadership, and problem-solving skills. LOCATION: Penang, Malaysia #LI-SJ1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.