Senior Researcher – analog and mixed-signal IC design using scaled CMOS

Ghent University – imec IDLab Design group Ghent University is one of the most important education and research institutions in the Low Countries, ranked 71 in the Academic Ranking of World Universities ( http://www.shanghairanking.com/ ). On a daily basis, over 15,000 staff members and 49,000 students implement its motto "Dare to Think". Ghent University's mission statement is characterized by qualitative education, internationally renowned research and a pluralistic social responsibility. The IDLab research group is also a core group of imec. Imec is the world-leading research and innovation hub in nanoelectronics and digital technologies. Imec is headquartered in Leuven, Belgium and also has distributed R&D groups at a number of Flemish universities, in the Netherlands, Taiwan, USA, China, and offices in India and Japan. All of these particular traits make IDLab a top-class research employer. Context The IDLab-Design group, of Ghent University and imec is seeking a Senior Researcher to conduct research and development in the area of ultra-high-speed wireline digital-to-analog conversion using advanced CMOS processes such as 5nm FinFET. Within imec, significant research is conducted across a set of multidisciplinary teams, focused on the realization of new generations of high-speed and optical transceivers, targeting baudrates far in excess of 100Gbaud. To achieve such rates, significant signal impairments originating from opto-electronic front-end bandwidth and non-linear distortion, RF interconnect and the fiber plant must be overcome. This can be done using sophisticated digital signal processing (DSP) algorithms, which in turn rely on ultra-high-speed analog-to-digital and digital-to-analog converters (ADCs and DACs), with sampling rates at least as high as the baudrate. These ADCs and DACs should be integrated into highly scaled CMOS nodes to keep the required power consumption and area small, and ensure sufficient performance to reach the necessary speed. What you will do You will join a team of integrated circuit (IC) design researchers who are working towards realization of wireline DAC prototypes using scaled CMOS (e.g. 5nm FinFET), with following tasks and responsibilities: Design state-of-the-art analog and mixed-signal IP in scaled CMOS nodes such as 5nm FinFET, in close collaboration with your team members, Execute the full design cycle from specification, over schematic, post-layout verification till documentation, using an ECAD environment set up for multi-person collaboration on the realization of an IP design library, up to a standard that these can be transferred to potential industrial customers, Contribute to the architectural definition of the IP, where necessary relying on abstract modelling tools, Support the testing of your IP blocks or test prototypes, this may include support for testboard development, or support during the measurements and characterisation, Coach and guide junior members of the IDLab-Design and imec teams, Interface with and report to customers and stakeholders, participate in design review meetings, build a good relationship with these customers and stakeholders, Keep your scientific and technical knowledge in the area of high-speed analog and mixed-signal IC design up to date, both from relevant literature, following trainings. The research targets are highly challenging, there is plenty of scope to generate and test innovative ideas focused on high-speed analog and mixed-signal IC design. What we do for you We provide you with the opportunity to join an enthusiastic team of researchers, postdocs and PhD students, which has an internationally recognized track record in the area of electronics underpinning diverse optical communication applications. We support you with the training necessary to develop your technical and personal skills. You will have the chance to provide input to the group’s internal roadmaps. We offer you the opportunity to design integrated circuits using the world’s most advanced CMOS processes: you can test your fabricated devices and IP in a state-of-the-art lab equipped with sophisticated measurement equipment. Who you are You have a PhD degree in Electrical Engineering or equivalent with a strong background in realization of analog and mixed-signal integrated circuits, At least 5 years design experience with a proven track record of successfully tested analog or mixed-signal integrated circuits, preferably using CMOS, FinFET or FDSOI processes, Proficiency with design tools such as Cadence, parasitic extraction and verification tools is a must, experience with electromagnetic modeling tools supporting RF will be considered a plus, You are motivated by addressing challenges that go far beyond the state-of-the-art, You are a teamplayer that integrates will into a multi-cultured and diverse team, fluency in English is essential, You are allowed to work in Belgium. Interested? Send your application (motivation letter and resume) or any questions concerning this vacancy to Peter Ossieur ( Peter.ossieur@imec.be )