Senior digital IC and verification engineer for high-speed wireline applications

Ghent University – imec IDLab Research group Ghent University is one of the most important education and research institutions in the Low Countries, ranked 71 in the Academic Ranking of World Universities ( http://www.shanghairanking.com/ ). On a daily basis, over 15,000 staff members and 49,000 students implement its motto "Dare to Think". Ghent University's mission statement is characterized by qualitative education, internationally renowned research and a pluralistic social responsibility. The IDLab research group is also a core group of imec. Imec is the world-leading research and innovation hub in nanoelectronics and digital technologies. Imec is headquartered in Leuven, Belgium and also has distributed R&D groups at a number of Flemish universities, in the Netherlands, Taiwan, USA, China, and offices in India and Japan. All of these particular traits make IDLab a top-class research employer. Context The IDLab-Design group, of Ghent University and imec is seeking a digital IC and verification engineer to conduct research and development in the area of digital signal processing for ultra-high-speed wireline applications. Within imec, significant research is conducted across a set of multidisciplinary teams, focused on the realization of new generations of high-speed and optical transceivers, targeting baudrates far in excess of 100Gbaud. To achieve such rates, significant signal impairments originating from opto-electronic front-end bandwidth and non-linear distortion, RF interconnect and the fiber plant must be overcome. This can be done using sophisticated digital signal processing (DSP) algorithms. These DSP algorithms should be integrated together with the analog front-end and high-speed analog-to-digital converter into highly scaled CMOS nodes to keep the required power consumption and area small, and ensure sufficient performance to reach the necessary speed. What you will do You will be part of a team of analog, digital, and mixed-signal integrated circuit (IC) design researchers who are working towards realization of wireline optical links using scaled CMOS (e.g. 5nm FinFET). You will study and implement DSP algorithms for high-speed wireline links, and validate the functionality and performance of the implemented algorithms. Your tasks will include: Implement the specifications into a system description in a power efficient way Create automated testbenches with a high functional verification coverage Create constraints and power intent files Synthesize the design (with or without power intent file) Perform logic equivalence checks Perform power estimations Run functional pre - and post layout simulations Adapt the internal scripting environment with gained knowledge Support the testing of your IP blocks or test prototypes, this may include support for testboard development, or support during the measurements and characterization Coach and guide junior members of the IDLab-Design and imec teams Interface with and report to customers and stakeholders, participate in design review meetings, build a good relationship with these customers and stakeholders Keep your scientific and technical knowledge in the area of high-speed digital and mixed-signal IC design up to date, both from relevant literature, following trainings, interactions with peers. What we do for you We provide you with the opportunity to join an enthusiastic team of researchers, postdocs and PhD students, which has an internationally recognized track record in the area of electronics underpinning diverse optical communication applications. We support you with the training necessary to develop your technical and personal skills. You will have the chance to provide input to the group’s internal roadmaps. We offer you the opportunity to design integrated circuits using the world’s most advanced CMOS processes: you can test your fabricated devices and IP in a state-of-the-art lab equipped with sophisticated measurement equipment Who you are We are looking for a self-motivated and creative team member; a quick learner eager to share his/her knowledge. In this position (s)he should have a good understanding of the ASIC (low power) design flow as well as the tools involved. System architecture knowledge and awareness of the IP available on the market would be an asset. You have a PhD degree in Electrical Engineering or equivalent with a strong background in realization of digital design/implementation and verification, You are proficient with design tools such as Cadence Genus, experience with Cadence Innovus or with UVM will be considered a plus, You have knowledge of scripting or programming languages like Tcl and Python, You are motivated by addressing challenges that go far beyond the state-of-the-art, You are a team player that integrates will into a multi-cultured and diverse team, fluency in English is essential, You are allowed to work in Belgium. Interested? If you want to apply, sent a CV and motivational letter to peter.ossieur@imec.be