Staff Silicon Design Engineer - DTCO & PDK Development

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: You will play a pivotal role in analyzing and optimizing semiconductor devices, ensuring robust performance under real-world conditions. Responsibilities include advanced DTCO of stdcell design, layout analysis, PDK management, DRC, LVS, PEX methodologies, capacitance modeling, EM analysis, IR Drop effects understanding, coupled with the ability to leverage Unix shell environments and scripting languages such as Perl and Python. This team is essential to the success of AMD as a growing company. It is a very exciting environment, and you will be working with the very best in our technology. You will be working on some of the most exciting projects the industry has to offer.   THE PERSON:  You will have in-depth knowledge of semiconductor device physics and fabrication processes, strong analytical and problem-solving skills related to semiconductor device performance, ability to collaborate effectively with design, layout, and verification teams, exceptional written and oral communication skills in English.   KEY RESPONSIBILITIES:  • Layout analysis for DTCO on Stdcells from foundry package and provide guidance/comment. • Interface with design teams (including Design, Enablement, CAD, Yield, Project Management) across AMD to capture Process Design Kit (PDK) requirements. • Develop and install key technology files which include DRC, LVS, Spice, PEX and EMIR • Design new regression tests to increase QA coverage of PDK. • Benchmark PDKs across various manufacturing partners (i.e. how does device performance compare?) • Create and monitor PDK testing and prevent design flow interruptions. • Communicate PDK requirements to foundry partners and negotiate release schedules. • Communicate and document all PDK releases to AMD design & enablement teams. • Ensure quick turn-around times to address all urgent PDK disruptions. • Triage PDK issues and drive to resolution.   PREFERRED EXPERIENCE:  • Expertise in DTCO of stdcell design and layout analysis. • Proficiency in industry-standard EDA (SNPS/CDNS/Siemens) tools for PDK, DRC, LVS, Virtuoso, parasitic resistance, capacitance extraction (PEX), capacitance modeling, and Electromigration (EM) and IR Drop (IR) analysis and reliability analysis. • Experience with IR Drop analysis techniques and tools. • Experience with SPICE simulation and familiarity with industry-standard modeling techniques. • Design for testing (DFT) engineer and PMs experience. • Proficiency in Unix shell environments, Perl, and Python scripting.   ACADEMIC CREDENTIALS:  • MSEE/MSCS or BSEE/BSCS with relevant years of experiences • Proven experience in DTCO of stdcells, PDK, DRC, LVS, PEX, EMIR analysis, DFT, and semiconductor designs. LOCATION: Seoul, Korea #LI-CC6 #LI-HYBRID #LI-D&I Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. THE ROLE: You will play a pivotal role in analyzing and optimizing semiconductor devices, ensuring robust performance under real-world conditions. Responsibilities include advanced DTCO of stdcell design, layout analysis, PDK management, DRC, LVS, PEX methodologies, capacitance modeling, EM analysis, IR Drop effects understanding, coupled with the ability to leverage Unix shell environments and scripting languages such as Perl and Python. This team is essential to the success of AMD as a growing company. It is a very exciting environment, and you will be working with the very best in our technology. You will be working on some of the most exciting projects the industry has to offer.   THE PERSON:  You will have in-depth knowledge of semiconductor device physics and fabrication processes, strong analytical and problem-solving skills related to semiconductor device performance, ability to collaborate effectively with design, layout, and verification teams, exceptional written and oral communication skills in English.   KEY RESPONSIBILITIES:  • Layout analysis for DTCO on Stdcells from foundry package and provide guidance/comment. • Interface with design teams (including Design, Enablement, CAD, Yield, Project Management) across AMD to capture Process Design Kit (PDK) requirements. • Develop and install key technology files which include DRC, LVS, Spice, PEX and EMIR • Design new regression tests to increase QA coverage of PDK. • Benchmark PDKs across various manufacturing partners (i.e. how does device performance compare?) • Create and monitor PDK testing and prevent design flow interruptions. • Communicate PDK requirements to foundry partners and negotiate release schedules. • Communicate and document all PDK releases to AMD design & enablement teams. • Ensure quick turn-around times to address all urgent PDK disruptions. • Triage PDK issues and drive to resolution.   PREFERRED EXPERIENCE:  • Expertise in DTCO of stdcell design and layout analysis. • Proficiency in industry-standard EDA (SNPS/CDNS/Siemens) tools for PDK, DRC, LVS, Virtuoso, parasitic resistance, capacitance extraction (PEX), capacitance modeling, and Electromigration (EM) and IR Drop (IR) analysis and reliability analysis. • Experience with IR Drop analysis techniques and tools. • Experience with SPICE simulation and familiarity with industry-standard modeling techniques. • Design for testing (DFT) engineer and PMs experience. • Proficiency in Unix shell environments, Perl, and Python scripting.   ACADEMIC CREDENTIALS:  • MSEE/MSCS or BSEE/BSCS with relevant years of experiences • Proven experience in DTCO of stdcells, PDK, DRC, LVS, PEX, EMIR analysis, DFT, and semiconductor designs. LOCATION: Seoul, Korea #LI-CC6 #LI-HYBRID #LI-D&I Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.