DFT Engineer

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Job Description: Responsibilities: • Execute scan insertion and ATPG pattern generation at block level, with exposure to top-level flows and increasing ownership based on experience • Perform ATPG generation and pattern simulation; verify test patterns and contribute to improving coverage and quality metrics. • Work with cross-functional teams including design, verification, and test engineering to identify and resolve DFT-related issues • Verify DFT circuitry and interface with other design blocks; debug timing and simulation issues with guidance as needed • Contribute to backend ATPG activities and test coverage improvements in support of yield and product quality objectives. • Apply industry-standard EDA tools (Tessent, Synopsys, Cadence) within established ATPG flows, and develop growing familiarity with FPGA-specific test methodologies. • Participate in efforts to improve test cost efficiency and coverage, contributing ideas and analysis as part of the broader DFT team. • Contribute to the development of HVM test content and participate in ATE bring-up activities, building knowledge of structural test techniques and DPM quality objectives. Requirements: • 1–5 years of experience in DFT concepts, scan architecture, and test methodology; strong academic grounding is equally considered for candidates at the junior end. • Understanding of test models (stuck-at, transition), pattern generation and verification, and fault simulation; deeper knowledge in these areas is an advantage • Hands-on experience or solid understanding of DFT scan insertion and ATPG generation; exposure through coursework, internship, or industry work is all considered. • Familiarity with EDA tools from Tessent, Synopsys, or Cadence; prior use in any professional or academic setting is valued, and willingness to expand tool expertise is expected. • Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field; involvement in a DFT flow through coursework, internship, or early industry experience is advantageous • Some exposure to ATE environments and silicon bring-up is a plus; familiarity with pattern formats or test program development is an added advantage • Strong analytical and problem-solving skills with a proactive approach to learning; interest in FPGA-specific DFT and fabric test techniques is a plus. Additional Information: This position requires a successful background and reference checks and satisfactory proof of your right to work in: Malaysia Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.