Advanced Packaging & Assembly Yield Analytics Engineer, Staff

Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: We are seeking a highly motivated and experienced engineer to join our team as an Advanced Packaging & Assembly Yield Analytics Engineer, Staff. In this role, you will drive yield analysis, yield learning, and manufacturing optimization for advanced packaging technologies, including 2.5D, 3DIC, chiplet-based architectures, and heterogeneous integration solutions. The ideal candidate will leverage large-scale manufacturing datasets, assembly process information, product test results, and package-level analytics to identify yield limiters, accelerate root-cause isolation, and improve product quality. You will work closely with OSATs, substrate suppliers, Product Engineering, Package Design, Reliability, and Manufacturing teams to enable successful product ramps and high-volume manufacturing. Key Responsibilities • Perform yield analytics and data-driven investigations across advanced packaging, assembly, and 3DIC manufacturing flows. • Analyze assembly, substrate, wafer, and electrical test data to identify yield loss mechanisms and manufacturing variations. • Develop methodologies to correlate package yield, assembly process parameters, substrate characteristics, and product test results. • Drive root-cause analysis and corrective actions through collaboration with OSATs, substrate suppliers, and cross-functional engineering teams. • Support New Product Introduction (NPI) and yield ramp activities through risk assessment, characterization, and yield monitoring. • Develop automated dashboards, KPIs, and reporting systems to monitor package manufacturing health and product quality. • Build predictive analytics and machine learning models to accelerate yield learning and proactively identify manufacturing risks. • Partner with Package Design, Product Engineering, Reliability, Quality, and Supply Chain teams to improve manufacturability and product robustness. • Define data requirements and analytics infrastructure for assembly and substrate manufacturing partners. • Drive continuous improvement initiatives to optimize yield, cycle time, quality, and manufacturing efficiency. Qualifications • M.S. or Ph.D. in Electrical Engineering, Materials Science, Applied Physics, Mechanical Engineering, Industrial Engineering, or a related field. • 5+ years of semiconductor industry experience in package engineering, assembly engineering, product engineering, yield engineering, or manufacturing analytics. • Strong understanding of semiconductor assembly processes, package structures, substrate technologies, and manufacturing flows. • Experience with yield analysis, statistical methods, root-cause investigation, and large-scale manufacturing data analytics. • Proficiency in JMP, Python, SQL, Power BI, Tableau, Excel, or equivalent analytical tools. • Demonstrated ability to solve complex technical problems using data-driven approaches. • Excellent communication skills and ability to work effectively across global and cross-functional teams. • Ability to travel to OSAT and manufacturing partner sites throughout Taiwan and Asia. Preferred Qualifications • Experience with advanced packaging technologies such as 2.5D, 3DIC, CoWoS, SoIC, Fan-Out, FCBGA, or chiplet-based architectures. • Experience working directly with OSATs, substrate suppliers, and high-volume manufacturing environments. • Knowledge of package reliability, failure analysis, and package qualification methodologies. • Familiarity with assembly process control, SPC methodologies, and manufacturing quality systems. • Experience applying AI/ML techniques to yield analysis and manufacturing optimization. • Proven track record of driving yield improvements and manufacturing excellence for advanced packaging technologies. Why Join Us This role offers a unique opportunity to shape the future of advanced semiconductor packaging technologies by driving yield learning, assembly optimization, and manufacturing analytics for next-generation 2.5D and 3DIC products. The successful candidate will play a key role in enabling cost-effective, high-quality, and scalable production of Qualcomm's most advanced packaging solutions. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. 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