Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, Machine Learning, APU, Server and Game consoles. NBIO global operates seamless from China, North America and Europe. IOHUB sits in the center of all data paths, it includes 2 foundation IP (name as IOHub Core and IOMMU) and one IOHUB Subsystem. IOhub Core is the PCI “host bridge” of the system which provides decoding and routing services to PCIe etc. devices. IOMMU (I/O Memory Management Unit) is responsible for address translation and memory protection, it plays a critical role on IO virtualization technology which is widely used in mega-data center. We are searching for a lead for IOHUB Subsystem verification and Project execution. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. • Strong team spirit • Drive to completion • Fluent verbal English KEY RESPONSIBLITIES: • IOHUB Subsystem verification strategy and scoping • IOHUB Subsystem test plan, DRVR implementation and verification closure • Closely work with Design/Architecture team to develop new verification components • Organize/attend conference call for strategy alignment, status sync up etc. with global team • Short term global travel if needed PREFERRED EXPERIENCE: • Global company working experience background, fluent oral English • Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT) is preferred. • Good knowledge of UVM/Verilog/System C/System Verilog. • Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA), insights into random techniques. • Experience of execution lead is an asset. • Experience of verification planning is an asset. • Knowledge of Virtualization is an asset. • Experience developing with AI assistants is a plus. • Strong scripting languages (Perl, C Shell, Makefile, …) experience. • Strong collaboration skill set ACADEMIC CREDENTIALS: • MSEE above 8 years, or BSEE above 9 years’ experience in digital ASIC/SOC design verification. • #LI-JW3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. THE ROLE: AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, Machine Learning, APU, Server and Game consoles. NBIO global operates seamless from China, North America and Europe. IOHUB sits in the center of all data paths, it includes 2 foundation IP (name as IOHub Core and IOMMU) and one IOHUB Subsystem. IOhub Core is the PCI “host bridge” of the system which provides decoding and routing services to PCIe etc. devices. IOMMU (I/O Memory Management Unit) is responsible for address translation and memory protection, it plays a critical role on IO virtualization technology which is widely used in mega-data center. We are searching for a lead for IOHUB Subsystem verification and Project execution. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. • Strong team spirit • Drive to completion • Fluent verbal English KEY RESPONSIBLITIES: • IOHUB Subsystem verification strategy and scoping • IOHUB Subsystem test plan, DRVR implementation and verification closure • Closely work with Design/Architecture team to develop new verification components • Organize/attend conference call for strategy alignment, status sync up etc. with global team • Short term global travel if needed PREFERRED EXPERIENCE: • Global company working experience background, fluent oral English • Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT) is preferred. • Good knowledge of UVM/Verilog/System C/System Verilog. • Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA), insights into random techniques. • Experience of execution lead is an asset. • Experience of verification planning is an asset. • Knowledge of Virtualization is an asset. • Experience developing with AI assistants is a plus. • Strong scripting languages (Perl, C Shell, Makefile, …) experience. • Strong collaboration skill set ACADEMIC CREDENTIALS: • MSEE above 8 years, or BSEE above 9 years’ experience in digital ASIC/SOC design verification. • #LI-JW3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.