Data Center GPU Performance Attainment Lead

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The successful candidate will assume responsibility for post-silicon activities related to performance characterization and optimization of AMD Datacenter products, spanning both single-node and multi-node deployments. THE PERSON: You have a passion for computer architecture, along with strong knowledge of HPC and ML workloads. You are a team player with excellent communication skills and experience collaborating with engineers across multiple sites and time zones. You are a quick learner, self-starter, and able to drive multiple complex tasks to completion. KEY RESPONSIBILITIES: • Develop and maintain automation frameworks for workload execution and performance data collection, enabling scalable and repeatable characterization across configurations. • Become a key stakeholder in the product power and performance definition process, ensuring alignment between architectural goals and measured silicon performance. • Develop, execute, and evolve performance characterization and optimization test plans across diverse usage scenarios, including High Performance Computing (HPC) and Machine Learning (ML) workloads. • Drive performance attainment for both scale-up (intra-node) and scale-out (multi-node) configurations, including:Multi-GPU scaling efficiency within a nodeInterconnect bandwidth utilization (e.g., XGMI / Infinity Fabric)Collective communication efficiency and communication-compute overlapWorkload scaling behavior (strong and weak scaling)Identification and mitigation of system-level bottlenecks across distributed environments • Analyze interactions between power management features and performance behavior, optimizing configurations to achieve the best performance and performance-per-watt tradeoffs. • Identify architectural and system-level bottlenecks and develop strategies to stress, expose, and mitigate worst-case performance scenarios. • Support prototyping and experimentation efforts to evaluate enhancements and new features that impact performance. • Debug and troubleshoot system-level issues across hardware, firmware, and software stacks observed in lab and production test environments. • Collaborate with cross-functional teams (architecture, firmware, drivers, platform, and workload teams) to drive root-cause analysis through to resolution and performance closure. • Proactively drive continuous improvement of post-silicon performance methodologies, tools, and workflows. PREFERRED EXPERIENCE: • Proven leadership skills with experience mentoring junior engineers, coordinating cross-functional teams, and driving complex performance characterization and optimization efforts across multiple locations. • Strong programming skills, with preference for Python and experience with ML frameworks (e.g., TensorFlow or PyTorch). • Proficiency in C/C++, scripting (Shell), and familiarity with performance tooling and automation workflows. • Strong understanding of computer architecture and system organization. • Deep knowledge of HPC and ML workloads, including scaling behavior and performance bottlenecks. • Experience with scale-up and scale-out performance analysis at rack-level and cluster-level deployments • Strong analytical and problem-solving skills, with a high level of attention to detail. • Excellent interpersonal, collaboration, and communication skills. ACADEMIC CREDENTIALS: • Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field. LOCATION: Austin, TX or Markham, ON This role is not eligible for visa sponsorship. #LI-HYBRID #LI-RL1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. THE ROLE: The successful candidate will assume responsibility for post-silicon activities related to performance characterization and optimization of AMD Datacenter products, spanning both single-node and multi-node deployments. THE PERSON: You have a passion for computer architecture, along with strong knowledge of HPC and ML workloads. You are a team player with excellent communication skills and experience collaborating with engineers across multiple sites and time zones. You are a quick learner, self-starter, and able to drive multiple complex tasks to completion. KEY RESPONSIBILITIES: • Develop and maintain automation frameworks for workload execution and performance data collection, enabling scalable and repeatable characterization across configurations. • Become a key stakeholder in the product power and performance definition process, ensuring alignment between architectural goals and measured silicon performance. • Develop, execute, and evolve performance characterization and optimization test plans across diverse usage scenarios, including High Performance Computing (HPC) and Machine Learning (ML) workloads. • Drive performance attainment for both scale-up (intra-node) and scale-out (multi-node) configurations, including:Multi-GPU scaling efficiency within a nodeInterconnect bandwidth utilization (e.g., XGMI / Infinity Fabric)Collective communication efficiency and communication-compute overlapWorkload scaling behavior (strong and weak scaling)Identification and mitigation of system-level bottlenecks across distributed environments • Analyze interactions between power management features and performance behavior, optimizing configurations to achieve the best performance and performance-per-watt tradeoffs. • Identify architectural and system-level bottlenecks and develop strategies to stress, expose, and mitigate worst-case performance scenarios. • Support prototyping and experimentation efforts to evaluate enhancements and new features that impact performance. • Debug and troubleshoot system-level issues across hardware, firmware, and software stacks observed in lab and production test environments. • Collaborate with cross-functional teams (architecture, firmware, drivers, platform, and workload teams) to drive root-cause analysis through to resolution and performance closure. • Proactively drive continuous improvement of post-silicon performance methodologies, tools, and workflows. PREFERRED EXPERIENCE: • Proven leadership skills with experience mentoring junior engineers, coordinating cross-functional teams, and driving complex performance characterization and optimization efforts across multiple locations. • Strong programming skills, with preference for Python and experience with ML frameworks (e.g., TensorFlow or PyTorch). • Proficiency in C/C++, scripting (Shell), and familiarity with performance tooling and automation workflows. • Strong understanding of computer architecture and system organization. • Deep knowledge of HPC and ML workloads, including scaling behavior and performance bottlenecks. • Experience with scale-up and scale-out performance analysis at rack-level and cluster-level deployments • Strong analytical and problem-solving skills, with a high level of attention to detail. • Excellent interpersonal, collaboration, and communication skills. ACADEMIC CREDENTIALS: • Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field. LOCATION: Austin, TX or Markham, ON This role is not eligible for visa sponsorship. #LI-HYBRID #LI-RL1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.