Layout Design, Sr Engineer in Da Nang
Da Nang, VietnamVerificationCompilersPhysical designSoC / ASICPosted Aug 21, 2026via html-list
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Layout Design, Sr Engineer in Da Nang
Da Nang, Da Nang, Vietnam
Engineering
Employee
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Overview
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
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Job Description
Date posted 08/20/2026
Category Engineering
Hire Type Employee
Job ID 18419
Date Posted 08/20/2026
Alternate Job Titles
• Custom Layout Engineer
• IC Layout Designer
• VLSI Layout EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent enough time in layout to know that the best designs do not happen by accident. They happen when someone understands what the circuit is trying to do and uses that understanding to make better placement, routing, and spacing decisions. You think about device matching, current density, and parasitic impact before you draw the first rectangle, not after DRC fails.You are the kind of engineer who looks at a schematic and sees the layout challenges before anyone asks. FinFET design rules do not scare you, they shape how you think about structure and symmetry. When LVS breaks, you do not guess. You trace nets, check hierarchies, and find the actual mismatch. Debugging does not frustrate you, it is part of the craft. You know that clean DRC and LVS are table stakes, the real work is making sure the layout supports the electrical intent without introducing problems three months later during characterization.At Synopsys, you will work on memory and standard cell layouts that ship in real products, and the decisions you make in Custom Compiler will show up in silicon across multiple process nodes.What You'll Be Doing
• Design custom layouts for memory and standard cell IP using Custom Compiler, translating circuit schematics into physical structures that meet performance, power, and area targets
• Run and debug physical verification flows using ICV or Calibre, resolving DRC, LVS, and ERC violations with an understanding of root cause
• Analyze layout parasitics and perform EMIR checks to ensure your designs meet electrical and reliability requirements
• Collaborate with circuit designers to understand design intent, device sizing, and matching requirements, then implement layouts that preserve those goals
• Build and refine layout cells that integrate cleanly into larger IP blocks, ensuring hierarchy, pin placement, and routing consistency
• Support bring-up and characterization activities by investigating layout-related issues flagged during post-silicon validationThe Impact You Will Have
• Deliver memory and standard cell layouts that meet aggressive performance, power, and area targets for leading-edge semiconductor markets
• Improve silicon quality and yield by catching layout-induced issues early, reducing the risk of costly respins
• Accelerate project schedules by automating layout tasks and verification flows
• Raise the bar for layout quality across the team by sharing best practices and debugging techniques
• Enable faster design iteration cycles by delivering clean, well-structured layouts that integrate smoothly with downstream teams
• Help define layout methodologies that scale across multiple process nodes and design familiesWhat You'll Need
• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field
• 2+ years of hands-on experience in custom layout, standard cell layout, or memory layout design
• Strong knowledge of MOSFET and FinFET device characteristics, P-N junctions, resistors, capacitors, antenna effects, and EMIR analysis
• Proficiency with Custom Compiler and physical verification using ICV, Calibre, or similar platforms
• Solid skills in DRC, LVS, and ERC debugging, with the ability to trace issues back to layout or netlist sourceWho You Are
• You approach layout with a designer's mindset, understanding circuit intent and using that knowledge to make better layout decisions
• You do not stop at clean DRC and LVS. You ask whether the layout actually supports the electrical performance the circuit needs
• You are comfortable working across tools and flows, moving between Custom Compiler, verification platforms, and parasitic extraction without losing momentum
• You communicate clearly with circuit designers and verification engineers, translating layout constraints into terms that help the team make better tradeoffsThe Team You'll Be Part OfYou will join a global engineering team focused on custom layout and physical design for memory and standard cell IP. The team works closely with circuit designers, verification engineers, and process technology partners to deliver high-performance layouts for advanced FinFET nodes.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
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Benefits
At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
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• Health & Wellness
Comprehensive medical and healthcare plans that work for you and your family.
• Time Away
In addition to company holidays, we have ETO and FTO Programs.
• Family Support
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• ESPP
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Retirement Plans
Save for your future with our retirement plans that vary by region and country.
• Compensation
Competitive salaries.
** Benefits vary by country and region - check with your recruiter to confirm
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Hiring Journey at Synopsys
Apply
When you apply to join us, your resume, skills, and experience are first reviewed for consideration.
Phone Screen
Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have.
Interview
Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role.
Offer
Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept!
Onboarding
There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation.
Welcome!
Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!
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Source URL: https://careers.synopsys.com/job/da-nang/layout-design-sr-engineer-in-da-nang/44408/99541955968