Staff Research Scientist, AI-Hardware Co-Design

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X. The Analog Garage is ADI’s Innovation Lab, located in the heart of downtown Boston. We pioneer breakthrough technologies to solve high-impact problems that drive tangible value. Bringing together engineers, research scientists, and business leaders, we develop new technologies and solutions in a fast-moving, experiment-focused startup atmosphere. The Role The Algorithmic Solutions Group develops cutting-edge, efficient algorithms to bring intelligence to the physical world. We fuse state-of-the-art machine learning with deep domain expertise to convert raw physical data into actionable insights, solving the hard problems where off-the-shelf solutions fall short. We are seeking a Staff Research Scientist, AI-Hardware Co-Design to architect the solutions that power the next generation of intelligent systems. Through rigorous analysis and proof-of-concepts, you will bridge the gap between advanced AI algorithms and hardware implementation to define the optimal compute strategy. Operating at the boundary of software and silicon, you will drive the co-design of algorithms and architecture, defining the computational foundation to enable physical intelligence. Key Responsibilities • Strategic Problem Definition: Collaborate with business leads and domain experts to identify opportunities where intelligent systems—integrating sensing, actuation, and tightly coupled algorithms—can solve previously impossible problems. You will focus on challenges that require holistic system innovation rather than just off-the-shelf components. • Research-to-Product: Lead technical execution from architectural design to validated proof-of-concept. You will partner with researchers and hardware engineers to bridge the gap between abstract research ideas and deployable solutions. • Feasibility analysis: Act as the "Physics of Compute" anchor for the research team. You will use high-fidelity simulation, modeling, and proof-of-concepts to quantify the impact of memory hierarchy, dataflow, and precision on system performance—distinguishing between viable product paths and impractical research concepts. • System-Level Architecture & Co-Design: Drive the simultaneous optimization of algorithms and hardware. You will treat the algorithm and the compute engine as a unified design space, adapting neural architectures to exploit specific hardware capabilities while selecting the optimal compute substrate—from ultra-low-power MCUs to custom accelerators—to meet strict power and area constraints. • Thought Leadership: Maintain a deep awareness of the evolving AI hardware and algorithm landscape. You will bring the best ideas from the academic and industrial communities into ADI, mentoring junior engineers and guiding the team toward state-of-the-art compute paradigms. The Ideal Candidate You are a Computer Architect with a deep appreciation for AI, or an AI Researcher with a deep understanding of silicon. You think in terms of data movement, memory bandwidth, and energy-per-operation. You understand that hardware constraints shape algorithmic innovation, just as algorithmic needs must dictate architectural choices. • Educational & Professional Background: You hold a PhD specialized in Computer Architecture or Integrated Circuit Design for AI workloads, and have 3+ years of industry experience applying architectural principles to real-world engineering constraints. • Deep System-Level Hardware Expertise: You possess a profound understanding of how to organize computation and data. You have demonstrated this by either leading the design of complex AI SoCs, or by validating novel architectures through rigorous, cycle-accurate simulation. You operate at the structural level of the machine, optimizing memory hierarchies, on-chip networks, and execution models to solve complex data movement and efficiency challenges. • Edge AI & Model Optimization: You possess deep expertise in hardware-aware deep learning. You are proficient in modern frameworks (PyTorch, JAX) and capable of training or fine-tuning models to validate architectural hypotheses. You go beyond standard backbones to master the optimal mapping of computational graphs to silicon, orchestrating dataflow, tiling, and quantization (INT8, mixed-precision) to maximize arithmetic intensity within strict edge power budgets. • Innovation Mindset: You navigate the ambiguity of early-stage innovation with creative persistence, translating open challenges into concrete technical roadmaps. You excel at decision-making under uncertainty, justifying how your architectural trade-offs directly address the problem and create value. You distinguish yourself with: • Proven Silicon Execution: You have successfully taped out a complex SoC or a custom AI accelerator. You understand the harsh reality of physical design—from timing closure to power delivery—and how these downstream constraints influence early-stage architectural decisions. • DSP & Signal Fluency: You are comfortable discussing Fourier transforms, noise floors, and sampling rates. You understand the intersection of classical Digital Signal Processing (DSP) and deep learning, capable of architecting systems where neural networks and traditional signal chains work in concert to extract information from noisy physical data. • Hands-on RTL Experience: Familiarity with Verilog/SystemVerilog or modern hardware construction languages (Chisel, PyMTL) is a strong plus, even if you will not be writing production RTL daily. • Strong publication record in top conferences and/or journals For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law. Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days The expected wage range for a new hire into this position is $172,000 to $236,500. • Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. • This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. • This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.