Sr Staff Engineer, Formal Verification
Bengaluru, IndiaRTL / HDLVerificationPhysical designSoC / ASICPosted Aug 11, 2026via html-list
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Sr Staff Engineer, Formal Verification
Bengaluru, Karnataka, India
Engineering
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Overview
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
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Job Description
Date posted 07/27/2026
Category Engineering
Hire Type Employee
Job ID 18152
Remote Eligible No
Date Posted 07/27/2026
Senior Staff Formal Verification EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent the better part of a decade proving that digital designs actually work, not just that they pass testbenches. Formal verification is where you live because you know that simulation can only show the presence of bugs, while formal methods can prove their absence. You have seen what happens when a corner case slips through, and you are the engineer who makes sure it does not.You understand RTL at a level that lets you read a design and immediately spot the edge cases that will break it. Temporal logic is not abstract theory to you, it is the language you use to describe what correct behavior actually means. You have worked with tools like Jasper or VC-Formal enough to know their strengths, their quirks, and when to push back on a proof that looks complete but is not.Mentoring comes naturally because you remember what it was like to debug your first failed assertion at 2am, and you would rather teach someone to set up a clean proof than fix their setup later. You can sit with a design team in Bangalore, walk through a formal verification plan, and leave them understanding not just what you are checking but why it matters.What You'll Be Doing
• Build and maintain an end-to-end formal verification flow that integrates cleanly into the broader verification process, not a standalone tool that lives in a corner
• Create formal verification plans that identify the key behaviors worth proving, then develop the assertions, assumptions, and cover properties that actually close on those behaviors
• Guide design and verification engineers on effective use of formal tools, reviewing setups and proofs to catch issues before they become blockers
• Maintain and extend assertion libraries that work for both simulation and formal contexts, ensuring consistency across verification approaches
• Apply formal techniques like bounded model checking, induction, and abstraction to prove correctness of complex RTL designs
• Debug RTL when proofs fail, tracing back from a counterexample to the root cause in the design or the verification environment
• Train team members and mentor junior engineers on formal methods, assertion-based verification, and debugging strategiesThe Impact You Will Have
• Catch design bugs that simulation would miss, preventing costly respins and schedule slips downstream
• Raise the quality bar for digital designs across Synopsys products by making formal verification a standard part of the process, not an afterthought
• Accelerate verification closure by proving corner cases formally instead of writing thousands of directed tests hoping to hit them
• Build verification infrastructure that other engineers can use effectively, multiplying your impact across the team
• Improve design quality at the source by working closely with RTL designers to identify and fix issues early
• Contribute to the silicon and IP solutions that power everything from AI accelerators to automotive systems
• Strengthen the formal verification capability of the Bangalore team through knowledge sharing and hands-on mentorshipWhat You'll Need
• 8+ years of industry experience in digital design or verification, with at least 5 years focused on formal verification techniques
• Deep understanding of digital logic, RTL design patterns, and the synthesis and timing flows that turn RTL into gates
• Hands-on experience with Verilog or SystemVerilog and the ability to read and debug complex RTL quickly
• Solid grasp of temporal logic and assertion-based verification, including SVA or PSL
• Experience with at least one formal verification tool such as Jasper or VC-Formal, including setup, proof strategies, and debug
• Track record of using formal methods to close verification on complex projects, not just toy examples
• Bachelor's or master's in computer science or electrical engineering; experience with Python, Perl, or Shell scripting is a plusWho You Are
• You can look at a failed proof, trace the counterexample back through the design, and figure out whether the bug is in the RTL, the assumptions, or the assertion itself
• You explain formal verification concepts to someone who has only done simulation-based verification in a way that makes them want to try it, not run away from it
• You push back when a verification plan is too vague or when assumptions are hiding real design issues instead of simplifying the problem space
• You stay organized across multiple verification tasks, keeping track of which proofs are complete, which are bounded, and which need more work
• You collaborate effectively with geographically distributed teams, whether that means a design review over video or a detailed written explanation of a proof strategy
• You mentor junior engineers by showing them how to think about formal verification, not just how to run a toolThe Team You'll Be Part OfYou will be part of the Solutions Group at the Bangalore Design Center, working with a team focused on delivering high-quality digital designs and verification solutions. The team values learning and growth, and you will have opportunities to work with talented engineers across different geographies and disciplines.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
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Benefits
At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
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• Health & Wellness
Comprehensive medical and healthcare plans that work for you and your family.
• Time Away
In addition to company holidays, we have ETO and FTO Programs.
• Family Support
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• ESPP
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Retirement Plans
Save for your future with our retirement plans that vary by region and country.
• Compensation
Competitive salaries.
** Benefits vary by country and region - check with your recruiter to confirm
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Hiring Journey at Synopsys
Apply
When you apply to join us, your resume, skills, and experience are first reviewed for consideration.
Phone Screen
Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have.
Interview
Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role.
Offer
Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept!
Onboarding
There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation.
Welcome!
Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!
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Source URL: https://careers.synopsys.com/job/bengaluru/sr-staff-engineer-formal-verification/44408/98407187136