Flying-BL enabled hierarchical SRAM arrays

This MSc project will investigate the design, modelling, and architectural evaluation of hierarchical SRAM arrays. As CMOS 2.0 pushes toward heterogeneous, functionally distributed system architectures, augmenting conventional silicon SRAM structures, enabling improved density, energy efficiency, and thermal spreading becomes mandatory. The work will focus on the co optimization between device characteristics and the underlying bitcell organization, reshaping the hierarchical memory organization. A central aspect of the project is the adaptation of conventional SRAM bitcell and peripheral circuits—including write drivers, sense amplifiers, wordline/bitline structures, and hierarchical sub array arrangements—to operate robustly with the new hierarchy. Type of Internship : Internship; Master internship; Combination of internship and thesis Master's degree : Master of Engineering Science Required educational background : Electrotechnics/Electrical Engineering Duration : >4 months University Promotor : Wim Dehaene (KU Leuven) For more information or application, please contact the supervising scientists Fernando Garcia Redondo ( fernando.garciaredondo@imec-int.com ), Pieter Weckx ( pieter.weckx@imec.be ) and Ankit Singh ( ankit.singh@imec.be )