SOC Engineering, Principal Engineer (STA)

Search Jobs Find Jobs For Where? Search Jobs SOC Engineering, Principal Engineer (STA) Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share • Email • LinkedIn • X • Facebook Jump to • Overview • Job Description • Benefits • Culture • How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Date posted 04/22/2026 Category Engineering Hire Type Employee Job ID 16909 Remote Eligible No Date Posted 04/22/2026 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.You Are: You are a passionate and driven STA Expert with a strong technical leadership and execution skills in Static Timing Analysis and design timing & power closure flows and methodologies. You have a proven ability to lead and deliver complex designs to tapeout. With at least 12 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges.Your expertise spans the entire timing closure spectrum—from constraints development, validation, static timing analysis (STA), power analysis, Timing & power ECO generation. You may also have good understanding and working experience of synthesis, and Formal verification. You have experience in both block-level and full-chip expertise, and you’re adept at developing and validating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like PrimeTime, PrimePower, PT-PX, PrimeClosure, Tweaker allowing you to deliver optimal solutions for high-frequency, low-power designs.Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organizational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.What You’ll Be Doing: Independently own and drive signoff static timing analysis and timing closure for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs. Execute static timing analysis (STA), power analysis, synthesis and timing/power closure to meet stringent performance and power targets. Develop and validate timing constraints at block-level or Full SoC level. Knowledge of synthesis, clock tree structures, implementation and STA tool correlation, impact of constraints on physical implementation, parasitic extraction, and formal verification will be preferred. Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence. Utilize and optimize Synopsys EDA tools, including PrimePower, PT-PX, PrimeClosure, and Tweaker to deliver state-of-the-art silicon solutions. Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency. Contribute to the continuous improvement of static timing analysis flows and methodologies and best practices, sharing insights and mentoring junior engineers as needed.The Impact You Will Have: Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide. Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations. Drive technical excellence and best practices within the team, influencing the future direction of static timing analysis and timing closure methodologies at Synopsys. Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise. Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction. Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes.What You’ll Need: Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field. 12+ years of relevant experience in static timing analysis, particularly in advanced technology nodes (7nm/5nm/3nm). Comprehensive hands-on experience of constraints development, validation, static timing analysis (STA), power analysis, Timing and power ECO generation. Proficiency with Synopsys EDA tools such as PrimeTime, PT-PX, PrimeClosure, Tweaker. Working experience with Synopsys tools like Fusion Compiler, Design Compiler, Formality, and StarRC. Strong scripting and automation skills using Python, PERL, TCL, or similar languages. Solid understanding of timing constraints development, validation, static timing analysis and closure, for both block-level and full-chip designs. Exposure to high-frequency design and low-power design methodologies.Who You Are: Proactive, self-motivated, and driven to achieve technical excellence. Exceptional problem-solving and analytical skills with a keen attention to detail. Excellent communication and interpersonal abilities, comfortable working in diverse and global teams. Collaborative team player who values knowledge sharing and mentoring others. Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.The Team You’ll Be A Part Of: You’ll join a world-class team of backend and static timing analysis engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share • Email • LinkedIn • X • Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page • Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. • Time Away In addition to company holidays, we have ETO and FTO Programs. • Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. • ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. • Retirement Plans Save for your future with our retirement plans that vary by region and country. • Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys! 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