ASIC Digital Design Engineer, Staff -Sr Staff

Search Jobs Find Jobs For Where? Search Jobs ASIC Digital Design Engineer, Staff -Sr Staff Tokyo, Tokyo, Japan Engineering Employee Apply Save Job Share • Email • LinkedIn • X • Facebook Jump to • Overview • Job Description • Benefits • Culture • How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Date posted 08/09/2026 Category Engineering Hire Type Employee Job ID 18307 Remote Eligible No Date Posted 08/09/2026 We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou are a digital design engineer who takes pride in delivering RTL that is not only functionally correct, but also clean, synthesizable, and ready for real silicon. You enjoy working through the details—timing, CDC, lint, and design quality—because you know they matter when IP ships in customer products.You work well in a collaborative, global environment. You communicate openly with design, verification, and implementation teammates, ask thoughtful questions when specs are unclear, and are willing to learn new tools and methodologies, including AI-driven design approaches. Whether you are deepening your expertise or guiding others through complex challenges, you bring ownership, curiosity, and a practical mindset to your work.What You'll Be Doing • Understand industry standards and functional specifications, and contribute to architecture and micro-architecture definitions for complex protocol IP cores • Design and implement RTL for digital blocks and subsystems in Verilog/SystemVerilog, balancing performance, area, power, synthesizability, and testability • Perform basic verification and collaborate with verification teams on test planning, assertion development, functional debug, and coverage closure • Perform RTL-level timing analysis during RTL development, and collaborate with implementation teams on STA, timing constraints, and synthesis as needed • Support CDC/RDC/Lint signoff readiness and collaborate on design-quality closure • Apply and explore AI-driven design tools and methodologies to improve design quality and automationThe Impact You Will Have • Your RTL will directly influence the quality and time-to-market of Synopsys IP used by semiconductor companies worldwide • You will reduce iteration cycles between front-end and back-end teams by delivering synthesis-ready, timing-aware designs • Your collaboration will catch issues earlier, reducing costly respins and late-stage fixes • The automation you build will improve design productivity for your team and beyond • Your attention to CDC/RDC/Lint readiness will strengthen product quality and reduce signoff riskWhat You'll Need • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field • 4~15+ years of experience in digital design and/or RTL development • Hands-on experience designing and implementing synthesizable RTL in Verilog/SystemVerilog, with understanding of performance, area, power, and testability tradeoffs • Experience with test planning, assertion development, basic verification, functional debug, and coverage closure • Experience performing RTL-level timing analysis, with practical understanding of STA, timing constraints, and synthesis • Experience with CDC/RDC/Lint signoff-ready design practices and design-quality closure • Scripting experience in Python, Tcl, Perl, or Shell • Written and oral communication skills in English and Japanese, with the ability to collaborate effectively across teamsNice to Have • Direct experience with PCIe or CXL IP design and development • Experience with low-power design and power intent development using UPF • Exposure to UVM or formal verification concepts • Exposure to functional safety concepts, ISO 26262, or FMEDA • Experience mentoring engineers or serving as a technical lead on RTL/IP development projects • Prior experience in a global product engineering environmentWho You Are • You take ownership of your work and follow through on issues until they are properly resolved • You collaborate openly across teams and communicate clearly in both Japanese and English • You stay curious and adapt quickly to new tools, flows, and technical challenges • You balance attention to detail with practical judgment—you know when to dig deep and when to ask for help • You share knowledge with teammates and contribute to a supportive, learning-oriented team cultureThe Team You'll Be Part OfYour recruiter will share more about the team structure and mission during the interview process.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share • Email • LinkedIn • X • Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page • Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. • Time Away In addition to company holidays, we have ETO and FTO Programs. • Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. • ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. • Retirement Plans Save for your future with our retirement plans that vary by region and country. • Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Tokyo View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys! BROWSE JOBS Find the open role that’s right for you Similar Jobs • Validation / Verification Engineer, Sr Staff -18261 Nepean, Canada • PCIe System Architect/ Principal Engineer-18290 Sunnyvale, California • ASIC Digital Design, Staff Engineer Bengaluru, India • Data Center Site Reliability Engineer Canonsburg, Pennsylvania Recently Viewed Jobs View all job opportunities here Saved Jobs View all job opportunities here View All Jobs Awards We're proud to receive several recognitions