DFT Application Engineer Manager

Engineer the Future with Us We currently have 424 open roles Innovation Starts Here Search Jobs Find Jobs For Where? Search Jobs DFT Application Engineer Manager Shanghai, Shanghai Municipality, China Apply Now Save Category Engineering Hire Type Employee Job ID 18450 Date posted 08/23/2026 Share this job • Email • LinkedIn • X • Facebook DFT Application Engineer ManagerLocation: ShanghaiWe Are:Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. We're looking for DFT Application Engineer Manager to join our Shanghai AE team. The AE manager works in a customer-oriented environment to deliver complex DFT flows and methodologies across varying industry segments like Autonomous Transportation, Mission critical AI, High performance computing and Mobile networking. The manager mainly interacts with the customers to assess their methodologies, flows, advance process node test chip and provides feedback to the TestMAX Product RD with customer DFT requirements and help to keep improving TestMAX products. Responsibilities may include a subset or all the following: • Leading Shanghai AE team to drive and win TestMAX engagements • Consultation for test solutions during design planning/budgeting. • Test methodology design rules checking during RTL coding stages. • Implementation of design for test (DFT) compression, automatic test generation (ATPG) for single stuck at (SSAF), Transition Delay Fault, Cell-aware faults, and other advanced fault models • Architects and implements solutions for built-in self-test (Memory and Logic BIST) circuitry to test devices in the field. • Participations in customer’s design and flow reviews. • Diagnostics study and debug. • Provides methodologies for test automation flow integration with design planning, RTL parser, scan synthesis, physical design, and sign-off verification tools (static timing, simulation, formal verification). • Develops white papers on methodology and other documentation as may be required for projects. • Provides technical consulting/expertise for customers operating Synopsys test automation tools in a wide variety of application scenarios.Key Qualifications • 8-10 years project DFT execution experience, team leadership experience is a plus for this position • Excellent soft skills on communication and cross team work experience • Excellent knowledge of Hardware Description Language (Verilog/VHDL) and RTL design • Excellent knowledge in scripting, TCL and Perl are preferred. • Ability and desire to dig into and solve complex parallel programming challenges. • Excellent debug and problem-solving skills • Excellent verbal and written communication skills • Excellent knowledge of the Linux OS and tools • Desire to learn and explore new technologies. • Design and verification experience are a plus. • Knowing Design-for-testing concept is a plus. • Prefer to have a long-term internship (9 or 18 months) and finish Master thesis in Synopsys is a plus.Preferred Experience • Familiar with Agentic AI development flow with Cursor, VS Code or other platform • Familiar with general IC design flow • Familiar with Verilog coding style and best practices • Familiar with VLSI implementation flow • Excellent English communication skill • Proficient users of Perl or TCL is preferred. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs • Staff Engineer - Physical Design Hyderabad, India Engineering • Senior Staff- Interface IP Verification (Pre-Silicon- PCIe/CXL/DDR/Ethernet) Bengaluru, India Engineering • Principal Engineer- Interface IP Verification (Pre-Silicon- PCIe/CXL/DDR/Ethernet) Bengaluru, India Engineering BROWSE JOBS Find the open role that’s right for you Similar Jobs • Staff Engineer - Physical Design Hyderabad, India • Senior Staff- Interface IP Verification (Pre-Silicon- PCIe/CXL/DDR/Ethernet) Bengaluru, India • Principal Engineer- Interface IP Verification (Pre-Silicon- PCIe/CXL/DDR/Ethernet) Bengaluru, India • Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet) Bengaluru, India Recently Viewed Jobs View all job opportunities here Saved Jobs View all job opportunities here View All Jobs