Software Engineer - FPGA Physical Implementation

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: AMD is looking for a software engineer to join our FPGA implementation tools team, focused on developing high-performance algorithms for next-generation device architectures. This role centers on improving placement, routing, and optimization capabilities within AMD’s FPGA toolchain. You will work on complex algorithmic problems that directly impact performance, scalability, and quality of results (QoR), while collaborating with a team of experts in FPGA architecture and software systems. Exposure to emerging areas such as Network-on-Chip (NoC) architectures is a plus. THE PERSON: The ideal candidate is a strong problem solver with a background in algorithms and software development, who thrives on tackling complex optimization challenges. You are comfortable working in a highly technical, collaborative environment and have the ability to break down difficult problems, develop efficient solutions, and clearly communicate your approach. Candidates with academic or industry experience in optimization, EDA, or related domains are especially encouraged to apply. KEY RESPONSIBILITIES: • Design, implement, and optimize algorithms for FPGA physical implementation tools, including placement, routing, and timing • Develop and enhance optimization techniques to improve QoR, runtime, and memory usage • Contribute to next-generation FPGA tool capabilities, including areas such as NoC-aware optimization and architecture modeling • Analyze performance bottlenecks and apply data-driven approaches to improve system efficiency • Collaborate closely with architecture, hardware, and software teams to deliver scalable solutions • Debug and resolve complex technical issues in large-scale codebases • Stay current with advancements in algorithms, EDA tools, and hardware/software co-design PREFERRED EXPERIENCE: • Strong programming skills in C/C++ • Solid foundation in data structures, algorithms, and problem solving • Experience with optimization techniques (e.g., heuristics, SAT, ILP, or related approaches) • Familiarity with concurrent or performance-oriented programming (multithreading) • Experience with development tools such as debuggers, profilers, and version control systems • Exposure to EDA tools, FPGA architecture, or digital design is a plus • Knowledge of Network-on-Chip (NoC) concepts is a plus • Background in graph theory, distributed systems, or large-scale optimization problems is a plus ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field. Advanced degrees (MS/PhD) with a focus on algorithms, optimization, or computer architecture are a plus. #LI-DR2 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. THE ROLE: AMD is looking for a software engineer to join our FPGA implementation tools team, focused on developing high-performance algorithms for next-generation device architectures. This role centers on improving placement, routing, and optimization capabilities within AMD’s FPGA toolchain. You will work on complex algorithmic problems that directly impact performance, scalability, and quality of results (QoR), while collaborating with a team of experts in FPGA architecture and software systems. Exposure to emerging areas such as Network-on-Chip (NoC) architectures is a plus. THE PERSON: The ideal candidate is a strong problem solver with a background in algorithms and software development, who thrives on tackling complex optimization challenges. You are comfortable working in a highly technical, collaborative environment and have the ability to break down difficult problems, develop efficient solutions, and clearly communicate your approach. Candidates with academic or industry experience in optimization, EDA, or related domains are especially encouraged to apply. KEY RESPONSIBILITIES: • Design, implement, and optimize algorithms for FPGA physical implementation tools, including placement, routing, and timing • Develop and enhance optimization techniques to improve QoR, runtime, and memory usage • Contribute to next-generation FPGA tool capabilities, including areas such as NoC-aware optimization and architecture modeling • Analyze performance bottlenecks and apply data-driven approaches to improve system efficiency • Collaborate closely with architecture, hardware, and software teams to deliver scalable solutions • Debug and resolve complex technical issues in large-scale codebases • Stay current with advancements in algorithms, EDA tools, and hardware/software co-design PREFERRED EXPERIENCE: • Strong programming skills in C/C++ • Solid foundation in data structures, algorithms, and problem solving • Experience with optimization techniques (e.g., heuristics, SAT, ILP, or related approaches) • Familiarity with concurrent or performance-oriented programming (multithreading) • Experience with development tools such as debuggers, profilers, and version control systems • Exposure to EDA tools, FPGA architecture, or digital design is a plus • Knowledge of Network-on-Chip (NoC) concepts is a plus • Background in graph theory, distributed systems, or large-scale optimization problems is a plus ACADEMIC CREDENTIALS: Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field. Advanced degrees (MS/PhD) with a focus on algorithms, optimization, or computer architecture are a plus. #LI-DR2 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.