FPGA Design Engineer - Hardware

FPGA Design Engineer - Hardware Download job offer in PDF format Renewable contract : Yes Level of qualifications required : Graduate degree or equivalent Other valued qualifications : PhD Fonction : Temporary scientific engineer About the research centre or Inria department The Inria Center at the University of Rennes is one of Inria’s eight research centers and is home to more than thirty research teams. The center is a major and internationally recognized player in the field of digital sciences. It is at the heart of a rich R&D and innovation ecosystem, bringing together highly innovative SMEs, large industrial groups, competitiveness clusters, research and higher education institutions, laboratories of excellence, and a technological research institute. Context The TARAN team at Inria and the University of Rennes is looking for passionate and motivated Digital Design Engineers seeking to make an impact in the fields of computer architecture and AI hardware accelerators. The right candidate will not be afraid to attack complex problems and assume broad ownership, ranging from chip or block architecture and programming models through RTL implementation, design verification, physical design, and DFT. Are you an experienced or young engineer interested in hardware design and looking for an exciting opportunity to advance your career? Join our team, where we design and verify hardware prototypes of processors and AI accelerators to support our research. We are seeking a creative and skilled colleague to help develop chips (ASICs) or FPGA prototypes. Are you looking for broader exposure across multiple IP designs? Do you want the opportunity to work globally within a recognized research team to deliver innovative systems? Join us to help shape the future of our research! Assignment As an FPGA hardware design engineer, you will design and develop complex digital systems using field-programmable gate arrays (FPGAs) for different hardware prototypes. Your goal will be to achieve maximum efficiency in power consumption, performance, and area while ensuring correct functional behavior. Your key responsibilities will include participating in the whole design flow: - Participating in defining the microarchitecture. - Developing system-level RTL code using System Verilog or VHDL. - Running design checks and identifying and fixing bugs. - Physical design (placement and routing) of the chip using the latest industrial methodologies and tools. - Back-end design and verification. Collaboration with researchers and engineers across the architecture, verification, performance analysis, power analysis, implementation, and various IP functions is essential to achieve success in our projects. Main activities You will be responsible for designing, implementing, and testing FPGA-based systems for a wide range of applications, such as security protocols and AI accelerators, among others. You will be involved in several research projects inside the TARAN team. Your main tasks are summarized below. * Define FPGA architecture and develop synthesizable RTL (VHDL or SV) for: - Communication protocols (e.g., USB). - Memory controllers. - AI accelerators such as systolic arrays. - Specific optimized arithmetic functions. - Fixed‑point digital signal processing as needed for filtering, estimation, or modulation. - Partition functions between FPGA, MCU/DSP, and other devices considering performance. - Select appropriate FPGA families and IP for timing‑critical and safety‑related functions. * Develop testbenches and simulations to verify your designs. * Perform static timing analysis and timing closure for: - Tight real‑time constraints. - Multiple clock domains and asynchronous interfaces. * Support lab and field testing: - Board bring‑up and system integration. - Debugging under real operating conditions using oscilloscopes, logic analyzers, current/voltage probes, and protocol analyzers. * Create and maintain documentation: - FPGA specifications, timing budgets, and interface definitions. - Verification plans, test reports, and release notes. * Support production and field updates (JTAG, in‑system programming, secure and fail‑safe update mechanisms). The position is for a one-year term, but it may be extended for up to 2 years. Skills Required Skills And Experience - You graduated from a University or Engineering School, in Computer Science, Computer Engineering or Electronic / Electrical Engineering - Solid understanding of SoC / FPGA design methodologies and techniques with hands-on experience of SoC design and integration for complex SoC - Experience in RTL design using Verilog, System Verilog or VHDL - Experience or knowledge in back-end design methodologies and tools (place and route) is a plus. - Knowledge of at least one full FPGA implementation flow. “Nice To Have” Skills And Experience - Have knowledge of AMBA protocol like AXI/AHB/APB/CHI - Understanding of memory controller, microprocessors, and debug architecture - Knowledge of basic scripting languages, e.g., Perl/TCL/Python - Experience with Linux, shell scripts, Makefiles, and repository management systems like GIT - Knowledge of hardware verification techniques - Familiar with embedded C, assembly, and compilers Benefits package • Subsidized meals • Partial reimbursement of public transport costs • Leave: 7 weeks of annual leave + 10 extra days off due to RTT (statutory reduction in working hours) + possibility of exceptional leave (sick children, moving home, etc.) • Possibility of teleworking (after 6 months of employment) and flexible organization of working hours • Professional equipment available (videoconferencing, loan of computer equipment, etc.) • Social, cultural and sports events and activities • Access to vocational training Remuneration monthly gross salary from 2695 euros according to diploma and experience Apply for this position Share • Facebook • Linkedin • Twitter • Email General Information • Theme/Domain : Architecture, Languages and Compilation Scientific computing (BAP E) • Town/city : Rennes • Inria Center : Centre Inria de l'Université de Rennes • Starting date : 2026-11-01 • Duration of contract : 12 months • Deadline to apply : 2026-09-30 Warning : you must enter your e-mail address in order to save your application to Inria. Applications must be submitted online on the Inria website. Processing of applications sent from other channels is not guaranteed. Instruction to apply Please submit online : your resume, cover letter and letters of recommendation eventually Defence Security : This position is likely to be situated in a restricted area (ZRR), as defined in Decree No. 2011-1425 relating to the protection of national scientific and technical potential (PPST).Authorisation to enter an area is granted by the director of the unit, following a favourable Ministerial decision, as defined in the decree of 3 July 2012 relating to the PPST. An unfavourable Ministerial decision in respect of a position situated in a ZRR would result in the cancellation of the appointment. Recruitment Policy : As part of its diversity policy, all Inria positions are accessible to people with disabilities. Contacts • Inria Team : TARAN • Recruiter : Sentieys Olivier / Olivier.Sentieys@irisa.fr About Inria Inria, the French national institute for research in digital science and technology, supports the French government in national research and innovation strategies in the digital field, acting as Digital Programs Agency. Inria leads over 300 research and innovation projects with its 3,500 scientists, engineers, and support staff, in partnership with universities and the digital ecosystem (businesses, entrepreneurs, and public stakeholders). Together, we explore strategic fields such as artificial intelligence, cybersecurity, quantum computing, cloud technologies, digital transformation in healthcare, digital twins, and digital technologies for defence. We develop practical solutions such as software, tech startups, partnerships with national companies, and cutting-edge training programmes. Our goal is to drive scientific, technological, and industrial excellence to ensure France’s digital sovereignty.