Principal Silicon Design Engineer (Design Automation)

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE ROLE: We are seeking an experienced engineer to lead the full-chip integration methodology for our FPGA and custom SoC programs. As the technical lead for the flow, you will define how IP and macro content, power/supply collateral, and signoff corners are integrated and verified across projects, and drive that methodology to adoption across the design and CAD teams. KEY RESPONSIBILITIES: • Lead and standardize the full-chip physical integration methodology across projects. • Consolidate and manage the IP/macro bill-of-materials and integration collateral (including power intent) into a verified integration package per project. • Define multi-corner signoff methodology and automation for new IP integration. • Serve as the cross-site technical point of reference for full-chip integration. PREFERRED EXPERIENCE: • Extensive experience in silicon physical design, integration, or signoff methodology on advanced nodes. • Strong expertise in RTL-to-signoff physical implementation (synthesis, place-and-route, static timing analysis) and IP/macro integration. • Solid understanding of bill-of-materials management and power intent (UPF). • Proven ability to define methodology that projects adopt and drive it across teams. • Proficient scripting (Tcl, Python, Perl). LOCATION: Penang, Malaysia #LI-FY #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. THE ROLE: We are seeking an experienced engineer to lead the full-chip integration methodology for our FPGA and custom SoC programs. As the technical lead for the flow, you will define how IP and macro content, power/supply collateral, and signoff corners are integrated and verified across projects, and drive that methodology to adoption across the design and CAD teams. KEY RESPONSIBILITIES: • Lead and standardize the full-chip physical integration methodology across projects. • Consolidate and manage the IP/macro bill-of-materials and integration collateral (including power intent) into a verified integration package per project. • Define multi-corner signoff methodology and automation for new IP integration. • Serve as the cross-site technical point of reference for full-chip integration. PREFERRED EXPERIENCE: • Extensive experience in silicon physical design, integration, or signoff methodology on advanced nodes. • Strong expertise in RTL-to-signoff physical implementation (synthesis, place-and-route, static timing analysis) and IP/macro integration. • Solid understanding of bill-of-materials management and power intent (UPF). • Proven ability to define methodology that projects adopt and drive it across teams. • Proficient scripting (Tcl, Python, Perl). LOCATION: Penang, Malaysia #LI-FY #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.