Systems Design Engineer - Memory Enablement

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE:  We are looking for a dynamic, energetic and a strong Enablement Engineer for Memory Enablement in Post silicon x86 environment, join our growing team. The successful candidate will work as part of the post-silicon validation group, enablement of memory features including training/margining and memory subsystem implementation, working with engineering teams across AMD and with the vendor eco-system. Candidate will be immersed in challenging work, developing and executing enablement and feature test plans and reports throughout the execution to meet project milestones at POR quality. The candidate should be able to work in a global environment while maintaining a synergetic culture.   THE PERSON:  As a key contribution to the success of AMD’s product, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry-leading technologies to market. In this role you will facilitate the enablement efforts of a program to ensure timely and qualitative completion of the milestones and adhere to the program commitments. KEY RESPONSIBILITIES: • Owning memory sub system implementation based on the Product requirements • Conducting day-to-day experiments for Memory enablement • Maintaining Test plans and reports and scrubbing the JIRA tickets on a periodic basis • Developing required test scripts for small tasks • Problem solving - the successful candidate loves debugging complex problems and has a track record of doing so • Work with the Memory Lead and senior members in refining the processes, and demonstrate keen interest to learn and explore new methods/ideas pertaining to memory subsystem PREFERRED EXPERIENCE:  • 8+ years of Memory enablement experience for any type of SoCs especially x86 containing multi core CPU/GPU subsystems with focus on memory technologies like DDR5/LPDDDR5 • Strong understanding of Memory Subsystem including the Memory PHY and Controller understanding, various DDR/LPDDr topologies and configurations, and ecosystem collaboration • Expertise in CPU subsystem in x86 / any SoC environment with Strong and Proven expertise in conducting tests and experiments towards enabling memory during Boot and Post -boot enablement • Good understanding of x86 HW, FW and BIOS Architecture • Strong communication and cross-functional collaboration abilities • Exposure to certain stages of Silicon Validation will be crucial, including use-case validation. • Practical experience of working on Processor based system designs is a plus • Knowledge of shell programming/scripting (e.g. Tcl Perl, Python etc.) • Hands-on experience dealing with Memory Analyzers   ACADEMIC CREDENTIALS:  • Bachelors or Masters degree in electrical or computer engineering #LI-SK3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. THE ROLE:  We are looking for a dynamic, energetic and a strong Enablement Engineer for Memory Enablement in Post silicon x86 environment, join our growing team. The successful candidate will work as part of the post-silicon validation group, enablement of memory features including training/margining and memory subsystem implementation, working with engineering teams across AMD and with the vendor eco-system. Candidate will be immersed in challenging work, developing and executing enablement and feature test plans and reports throughout the execution to meet project milestones at POR quality. The candidate should be able to work in a global environment while maintaining a synergetic culture.   THE PERSON:  As a key contribution to the success of AMD’s product, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry-leading technologies to market. In this role you will facilitate the enablement efforts of a program to ensure timely and qualitative completion of the milestones and adhere to the program commitments. KEY RESPONSIBILITIES: • Owning memory sub system implementation based on the Product requirements • Conducting day-to-day experiments for Memory enablement • Maintaining Test plans and reports and scrubbing the JIRA tickets on a periodic basis • Developing required test scripts for small tasks • Problem solving - the successful candidate loves debugging complex problems and has a track record of doing so • Work with the Memory Lead and senior members in refining the processes, and demonstrate keen interest to learn and explore new methods/ideas pertaining to memory subsystem PREFERRED EXPERIENCE:  • 8+ years of Memory enablement experience for any type of SoCs especially x86 containing multi core CPU/GPU subsystems with focus on memory technologies like DDR5/LPDDDR5 • Strong understanding of Memory Subsystem including the Memory PHY and Controller understanding, various DDR/LPDDr topologies and configurations, and ecosystem collaboration • Expertise in CPU subsystem in x86 / any SoC environment with Strong and Proven expertise in conducting tests and experiments towards enabling memory during Boot and Post -boot enablement • Good understanding of x86 HW, FW and BIOS Architecture • Strong communication and cross-functional collaboration abilities • Exposure to certain stages of Silicon Validation will be crucial, including use-case validation. • Practical experience of working on Processor based system designs is a plus • Knowledge of shell programming/scripting (e.g. Tcl Perl, Python etc.) • Hands-on experience dealing with Memory Analyzers   ACADEMIC CREDENTIALS:  • Bachelors or Masters degree in electrical or computer engineering #LI-SK3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.