Staff Software Development Engineer

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Job Description: Lattice is seeking candidates for the position of Staff Software Development Engineer in FPGA place and route. This is a full-time position located in Pune, India. Summary: The successful candidate will be part of a dynamic team responsible for designing and developing Lattice FPGA software tools, with a strong focus on place and route engine development. They will contribute to delivering high-performance software solutions that support advanced security workflows like Isolation Design Flow for FPGA design, emphasizing optimization of QoR metrics such as performance, area, runtime, and memory utilization across various FPGA architectures. Collaborating closely with other developers, the candidate will help build and enhance place and route tools for multiple FPGA product lines. Responsibilities also include supporting customer needs, developing new software features, maintaining existing tools, and working cross-functionally to deliver integrated, value-added solutions. Accountabilities: • Candidate will work on developing advanced security flows, like Isolation Design Flow • Responsible for place and route engine quality improvement • Responsible for place and route feature and capability development • Responsible for Lattice new FPGA product support • Create unit tests to validate implementation and ensure high quality Qualifications: • BS/MS/PhD in Electrical Engineering or Computer Science or Computer Engineering • Proficient with C/C++, data structure, graph algorithms, logic design and shell scripts • Strong background and experience in data structures and algorithms • Experience of place and route engine development in either FPGA or ASIC domain is a must • Experience of FPGA place and route engine development is ideal • Strong written and verbal communication skills, and collaboration skill • Experience of multi-processing development is a plus • Solid understanding in FPGA architectures is a plus • 10+ years of experience in EDA tool (preferably, place and route) development • Additional Information: This position requires a successful background and reference checks and satisfactory proof of your right to work in: India Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.