ASIC Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role: The MSIP UMC team is looking for an ASIC Design Verification Engineer to join our growing team. We develop leading-edge DDR technologies powering data center and machine learning workloads. This team is part of the development for tomorrow’s client, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP verification starting from helping to create a verification architecture, defining test plans, verification environment development, and verification closure/sign-off. You will be taking part in key technical leadership activities and collaborating with DV Architects and DV leads in shaping cutting verification environments for current and future programs. As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. The Person: Strong analytical thinking and problem-solving skills, excellent attention to detail. Possesses good teamwork, communication and interpersonal skills A self-starter and able to independently drive tasks to completion Enjoy working in a fast-paced, multi-project team environment using state-of-the-art tools and technology Possesses a continuous improvement mind-set Key Responsibilities: • Collaborate with IP architects to come up with verification architecture, verification methodology, improvements, and development plans • Taking on some key technical leadership responsibilities to help current DV leads and DV Architects • Participate in verification of complex IP blocks and take end-to-end ownership of key features for all projects • Work on test plans, verification environment development, regression, and coverage closure • Develop modifying and maintaining VIP, libraries, verification environments, testcases (random and directed) using System Verilog/UVM/SystemC • Triaging and Debugging Regressions • Analyzing code and functional coverage • Deploying industry-leading verification methodologies such as UVM and formal Verification • Reproducing functional bugs found in post-silicon in dynamic simulation and/or formal verification environments • Conducting and participating in code reviews • Develop and maintain scripts and tools to continuously improve in engineering infrastructure, methodology and execution Preferred Experience: • ASIC verification experience • Strong understanding of digital design and computer architecture • Strong understanding and experience in block-level constrained random verification • Proficient in Verilog, System Verilog, C/C++, UVM, OOP, and working in Linux and Windows environments • ASIC design knowledge and be able to debug System Verilog RTL code using simulation tools • Experience in formal verification would be an asset Academic Credentials: • BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science. This role is not eligible for visa sponsorship. #LI-DP1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. The Role: The MSIP UMC team is looking for an ASIC Design Verification Engineer to join our growing team. We develop leading-edge DDR technologies powering data center and machine learning workloads. This team is part of the development for tomorrow’s client, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP verification starting from helping to create a verification architecture, defining test plans, verification environment development, and verification closure/sign-off. You will be taking part in key technical leadership activities and collaborating with DV Architects and DV leads in shaping cutting verification environments for current and future programs. As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. The Person: Strong analytical thinking and problem-solving skills, excellent attention to detail. Possesses good teamwork, communication and interpersonal skills A self-starter and able to independently drive tasks to completion Enjoy working in a fast-paced, multi-project team environment using state-of-the-art tools and technology Possesses a continuous improvement mind-set Key Responsibilities: • Collaborate with IP architects to come up with verification architecture, verification methodology, improvements, and development plans • Taking on some key technical leadership responsibilities to help current DV leads and DV Architects • Participate in verification of complex IP blocks and take end-to-end ownership of key features for all projects • Work on test plans, verification environment development, regression, and coverage closure • Develop modifying and maintaining VIP, libraries, verification environments, testcases (random and directed) using System Verilog/UVM/SystemC • Triaging and Debugging Regressions • Analyzing code and functional coverage • Deploying industry-leading verification methodologies such as UVM and formal Verification • Reproducing functional bugs found in post-silicon in dynamic simulation and/or formal verification environments • Conducting and participating in code reviews • Develop and maintain scripts and tools to continuously improve in engineering infrastructure, methodology and execution Preferred Experience: • ASIC verification experience • Strong understanding of digital design and computer architecture • Strong understanding and experience in block-level constrained random verification • Proficient in Verilog, System Verilog, C/C++, UVM, OOP, and working in Linux and Windows environments • ASIC design knowledge and be able to debug System Verilog RTL code using simulation tools • Experience in formal verification would be an asset Academic Credentials: • BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science. This role is not eligible for visa sponsorship. #LI-DP1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.