High Speed IO Analog Mixed Signal Architect/ Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Be part of AMD’s analog/mixed signal IP design team responsible for the design and development of next generation IOs, high speed memory (LPDDRx, gDDRx, HBMx) and die-to-die Gbps proprietary PHY IP solutions. Establishes and maintains AMD’s technological leadership position in analog circuit architecture and design with a proven track record for problem solving and innovation. THE PERSON: The ideal candidate has experience leading others in technical settings. You also have excellent communication, writing, and presentation skills.  KEY RESPONSIBLITIES: • High Speed IO/DDR/die-to-die (d2d)/SerDes AMS circuit architecture and design • Lead Definition, review and sign-off on analog/mixed signal IP top level architecture and component/circuit level specifications • Work and collaborate with System/Platform & SOC architects to translate system level specs to AMS blocks/circuit level specifications. • Author AMS blocks circuit and architecture technical specifications, AMS pre-silicon verification, AMS post-silicon characterization/validation test plans. • Supervise pre-silicon layout, post-silicon characterization and debug. • Support product bring-up and debug, and Sign-off on test-plans and characterization reports PREFERRED EXPERIENCE: • Hand-on design experience in multi-Gbps serial interfaces (PCIE, USB, …), parallel high BW memory interface PHY/IOs (LPDDRx, HBM, gDDR, …) and die-to-die/chip-to-chip links PHY IPs • Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for receiver/transmitter and PLL/DLL/clocking. In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques • Solid experience of designing and architecting analog mixed-signal circuit blocks including DLLs, phase interpolator, low jitter clock distribution, bandgap, biasing circuits, LDO regulators, amplifiers, comparators. Experience in mixed signal design circuit blocks such as digital/analog DLLs, duty cycle corrector, clock and data recovery, clock mixer, … • Solid Understanding of high-speed IO signaling topologies and architectures including system-silicon co-design/co-optimizations for best in class PPA. • Solid understanding of high speed IO link budget analysis and jitter/SNR metrics and design trades. • Experience in low power design techniques for high speed/custom digital circuit (e.g. CMOS/CML high speed design for counters, dividers, …) design and analysis including transistor level timing sign-off • Solid understanding of power, area and performance trade-offs in mixed signal IP design • Design Experience in FinFet advanced CMOS process nodes 16nm/7nm/3nm and below coupled with a solid understanding of transistor device performance and fundamentals • Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools • Work with project-manager, system architects, IC designers and physical designers to guarantee quality/timely deliverables meeting project’s schedule and technical requirements • Analytical thinking, inventive, and Quality-oriented mindset. Strong and effective technical and management communication at the peer and upward management levels. • Track record of successfully taking AMS designs to production • Excellent written and verbal communication skills able to operate without direct supervision but also work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic/fast-paced environment. • Exhibit strong initiative and ownership of tasks and responsibilities. Seek help proactively as well as share and pass on knowledge ACADEMIC CREDENTIALS: • MS or PhD in Electrical, Computer Engineering or related equivalent LOCATION: San Jose, anywhere in California This role is not eligible for visa sponsorship. #LI-TB2 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. THE ROLE: Be part of AMD’s analog/mixed signal IP design team responsible for the design and development of next generation IOs, high speed memory (LPDDRx, gDDRx, HBMx) and die-to-die Gbps proprietary PHY IP solutions. Establishes and maintains AMD’s technological leadership position in analog circuit architecture and design with a proven track record for problem solving and innovation. THE PERSON: The ideal candidate has experience leading others in technical settings. You also have excellent communication, writing, and presentation skills.  KEY RESPONSIBLITIES: • High Speed IO/DDR/die-to-die (d2d)/SerDes AMS circuit architecture and design • Lead Definition, review and sign-off on analog/mixed signal IP top level architecture and component/circuit level specifications • Work and collaborate with System/Platform & SOC architects to translate system level specs to AMS blocks/circuit level specifications. • Author AMS blocks circuit and architecture technical specifications, AMS pre-silicon verification, AMS post-silicon characterization/validation test plans. • Supervise pre-silicon layout, post-silicon characterization and debug. • Support product bring-up and debug, and Sign-off on test-plans and characterization reports PREFERRED EXPERIENCE: • Hand-on design experience in multi-Gbps serial interfaces (PCIE, USB, …), parallel high BW memory interface PHY/IOs (LPDDRx, HBM, gDDR, …) and die-to-die/chip-to-chip links PHY IPs • Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for receiver/transmitter and PLL/DLL/clocking. In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques • Solid experience of designing and architecting analog mixed-signal circuit blocks including DLLs, phase interpolator, low jitter clock distribution, bandgap, biasing circuits, LDO regulators, amplifiers, comparators. Experience in mixed signal design circuit blocks such as digital/analog DLLs, duty cycle corrector, clock and data recovery, clock mixer, … • Solid Understanding of high-speed IO signaling topologies and architectures including system-silicon co-design/co-optimizations for best in class PPA. • Solid understanding of high speed IO link budget analysis and jitter/SNR metrics and design trades. • Experience in low power design techniques for high speed/custom digital circuit (e.g. CMOS/CML high speed design for counters, dividers, …) design and analysis including transistor level timing sign-off • Solid understanding of power, area and performance trade-offs in mixed signal IP design • Design Experience in FinFet advanced CMOS process nodes 16nm/7nm/3nm and below coupled with a solid understanding of transistor device performance and fundamentals • Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools • Work with project-manager, system architects, IC designers and physical designers to guarantee quality/timely deliverables meeting project’s schedule and technical requirements • Analytical thinking, inventive, and Quality-oriented mindset. Strong and effective technical and management communication at the peer and upward management levels. • Track record of successfully taking AMS designs to production • Excellent written and verbal communication skills able to operate without direct supervision but also work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic/fast-paced environment. • Exhibit strong initiative and ownership of tasks and responsibilities. Seek help proactively as well as share and pass on knowledge ACADEMIC CREDENTIALS: • MS or PhD in Electrical, Computer Engineering or related equivalent LOCATION: San Jose, anywhere in California This role is not eligible for visa sponsorship. #LI-TB2 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.