Graduate - Design Verification Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Graduate - Design Verification Engineer THE ROLE: As a Silicon Design Engineer, you will work closely with verification experts and designers to verify a variety of DDR Subsystems that incorporates multiple DDR/LPDDR controllers, PHYs, clock IPs and other compenents. This will be leveraging UVM and also Formal proofs. This role is a lauch pad into executing roles that will give plenty of scope for career progression and personal development in the future. The first role is the key role to be able to learn alongside local experts and evolve as an engineer.   THE PERSON: You have a passion for compelx digital design, and verification in general. You work on evolving as a team player with excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and are ready to take on problems. KEY RESPONSIBILITIES: • Drive verification for a design as well as write formal properties and assertions to verify designs • Coordinate with RTL engineers to implement logic design for better clock gating and verify all the various aspects of the design • Write tests, sequences, and testbench components in SystemVerilog and UVM along with Formal to achieve the complete verification of the design • Responsible for verification quality metrics like pass rates, code coverage and functional coverage PREFERRED EXPERIENCE: • Project level experience with design concepts and RTL implementation or verification during an earlier internship • Experience or familiarity with Formal tools or Functional verification tools like VCS • Having crafted designs or testbenches in Verilog or System-Verilog ACADEMIC CREDENTIALS: • Bachelors or Masters degree in Electronics/Computer/Electrical Engineering • A track record in univierity of consistent high grades especially with subject specialization and project work #LI-PL1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. Graduate - Design Verification Engineer THE ROLE: As a Silicon Design Engineer, you will work closely with verification experts and designers to verify a variety of DDR Subsystems that incorporates multiple DDR/LPDDR controllers, PHYs, clock IPs and other compenents. This will be leveraging UVM and also Formal proofs. This role is a lauch pad into executing roles that will give plenty of scope for career progression and personal development in the future. The first role is the key role to be able to learn alongside local experts and evolve as an engineer.   THE PERSON: You have a passion for compelx digital design, and verification in general. You work on evolving as a team player with excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and are ready to take on problems. KEY RESPONSIBILITIES: • Drive verification for a design as well as write formal properties and assertions to verify designs • Coordinate with RTL engineers to implement logic design for better clock gating and verify all the various aspects of the design • Write tests, sequences, and testbench components in SystemVerilog and UVM along with Formal to achieve the complete verification of the design • Responsible for verification quality metrics like pass rates, code coverage and functional coverage PREFERRED EXPERIENCE: • Project level experience with design concepts and RTL implementation or verification during an earlier internship • Experience or familiarity with Formal tools or Functional verification tools like VCS • Having crafted designs or testbenches in Verilog or System-Verilog ACADEMIC CREDENTIALS: • Bachelors or Masters degree in Electronics/Computer/Electrical Engineering • A track record in univierity of consistent high grades especially with subject specialization and project work #LI-PL1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.