[NanoIC topic] Investigation of write reliability in spin orbit torque-driven MRAM

The rapid growth of AI-driven applications today is pushing conventional charge-based memory technologies to their limits due to the concerns in reliability, scalability, and volatility. This pushes a pressing need for alternative memory solutions that offer faster operation, higher endurance, and non-volatile data storage. Spintronics, which leverages the electron’s spin in addition to its charge, offers a promising pathway for next-generation memory technologies. Magnetic Random-Access Memory (MRAM) combines these advantages, offering high endurance and fast read/write speeds, making it a strong candidate for future memory technologies. Spin–Orbit Torque MRAM (SOT-MRAM) is one of the most promising MRAM concepts with demonstrated reliability of its constituent magnetic tunnel junction (MTJ) devices up to 10 15 – 10 18 cycles for ultra-low write latencies down to 200 ps, thereby making it an attractive proposition for future AI-ready compute and high performance systems [1]. To advance SOT-MRAM toward practical applications, it is essential to enable deterministic write schemes, low power read/write operations, high endurance and application-relevant data retention metrics. The benefits of reliable magnetization switching at low currents are multi-fold, as it directly improves energy efficiency, device reliability, and endurance. To ensure reasonable data retention, the MTJ stacks are engineered to have strong perpendicular magnetic anisotropy, thus enabling reliable data storage with good data integrity. However, the switching current is typically inversely related to retention in conventional MRAM technology, creating a fundamental trade-off. Therefore, understanding the relationship between switching current and magnetic anisotropy and thermal stability is crucial for designing energy-efficient, nanoscale SOT-MRAM devices and guiding future material development. The aim of this internship is to investigate the impact of material systems and device design engineering on the switching/write reliability and its correlation with the thermal stability (= data retention) of SOT-MRAM cells using advanced electrical characterization techniques. This work will focus on elucidating the relationship between switching current and retention and, if time permits, its evolution at reduced device dimensions. By studying the underlying switching mechanisms through advanced electrical and physical characterization, this internship will contribute to enabling reliable switching in nanoscale SOT-MRAM and advancing scalable, energy-efficient memory technologies. We seek a candidate with a physics or engineering background, a strong interest in experimental work, and a passion for cutting-edge science and technology, particularly in the fast-growing area of memory technology. References: https://www.nature.com/articles/s44306-024-00044-1 Type of internship : Master internship Duration : 6 - 9 months Required educational background : Electrotechnics/Electrical Engineering, Materials Engineering, Nanoscience & Nanotechnology, Physics University promotor : Kristiaan Temst (KU Leuven) Supervising scientist(s) : For further information or for application, please contact Siddharth Rao ( Siddharth.Rao@imec.be ) and Van Dai Nguyen ( Van.Dai.Nguyen@imec.be ) The reference code for this position is 2026-INT-105 . Mention this reference code in your application. Only for self-supporting students. Applications should include the following information: resume motivation current study Incomplete applications will not be considered