About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFiv
Verification jobs 3,636
Design verification and validation — UVM, formal methods and testbench engineering.
Filter all 3,636 Verification roles →- Santa Clara, California, United StatesRISC-VRTL / HDLVerificationAug 30, 2026
- Santa Clara, California, United StatesRISC-VVerificationAug 30, 2026
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFiv
- VerificationSoC / ASICAug 30, 2026
- Toronto, CanadaVerificationAug 30, 2026
- VerificationAug 30, 2026
- VerificationAug 30, 2026
Verification Engineer
Speedata
VerificationAug 30, 2026- VerificationAug 30, 2026
Digital Verification Engineer
Snowcap Compute
Design VerificationVerificationAug 30, 2026- 深圳、上海、北京、西安、成都RTL / HDLVerificationSoC / ASICAug 30, 2026
岗位职责: • 参与智能网卡芯片IP级或SOC级功能验证; • 与IC设计工程师沟通,参与所负责的IP或SOC验证功能点分解和验证计划制定; • 基于UVM验证方法学,参与所负责IP或SOC级别的仿真验证环境搭建; • 使用SystemVerilog和C语言开发测试向量并进行回归测试; • 参与计划及实施各种覆盖率分析。 任职要求: • 熟悉 system Verilog, UVM 以及 formal 验证方法; • 有开发 scalable and port
Verification Engineer
Semidynamics Technology Services, S.L.
VerificationAug 30, 2026Infrastructure Verification Engineer
Semidynamics Technology Services, S.L.
VerificationAug 30, 2026Senior Formal Verification Engineer - Vector Unit (VU)
Semidynamics Technology Services, S.L.
VerificationAug 30, 2026Senior Verification Engineer - Core Testbench & DV Methodology Lead
Semidynamics Technology Services, S.L.
VerificationAug 30, 2026Senior Verification — LSU (Load/Store Unit) and Data Cache
Semidynamics Technology Services, S.L.
VerificationAug 30, 2026SoC Design Verification Engineer
Rebellions
VerificationSoC / ASICAug 30, 2026IP Design Verification Engineer
Rebellions
VerificationAug 30, 2026- Barcelona, Barcelona/Catalunya/Espanya, SpainVerificationSecurityAug 30, 2026
Build the Future of Confidential AI What if the next breakthrough in AI wasn't just faster, but fundamentally more trusted? At Openchip, we're building the secure computing platforms that will power the next generation of AI. If you're pa
- Roma, ItalyRISC-VRTL / HDLVerificationAug 30, 2026
The Role: As a Physical Design Senior Engineer, you will take technical ownership of the implementation for highly complex digital blocks, including high-speed interfaces, mixed-signal control logic, and automotive low-power modules. Worki
- Barcelona, Barcelona/Catalunya/Espanya, SpainRISC-VRTL / HDLVerificationAug 30, 2026
The Role: We are actively seeking a Silicon Design Framework and Emulation-Prototyping Engineer to join our dynamic and growing Hardware Design team. The mission of the role is to enable fast, reliable, and scalable hardware-software co-de
- Barcelona, Barcelona/Catalunya/Espanya, SpainRTL / HDLVerificationSoC / ASICAug 30, 2026
The Role: As a Senior Formal Verification Engineer, you will contribute to defining and leading the formal verification strategy for our systems. Responsibilities: · Work closely with system architects and design team to establish formal
- Barcelona, Barcelona/Catalunya/Espanya, SpainRISC-VVerificationKernel / LinuxAug 30, 2026
The Role: Openchip is building new RISC-V chips with security at heart, enabling safer and more privacy-respectful execution of data processing workloads like AI models. As a Senior Offensive Security Engineer, you will help to ensure that
RAS Hardware Architect
OpenChip
Barcelona, Barcelona/Catalunya/Espanya, SpainRISC-VVerificationFirmwareAug 30, 2026The SoC Architecture team is responsible for defining high-performance and power efficient System-on-Chip hardware architecture. The team identifies Hardware Requirements, defines the overall SoC system and delivers High-level Architecture
- Barcelona, Barcelona/Catalunya/Espanya, SpainRISC-VVerificationFirmwareAug 30, 2026
The Security I/O Hardware Design team leads innovation, development, and integration of advanced security features and I/O solutions across a diverse product portfolio. The team operates within the Hardware Design Group, with two primary m
Staff CPU Architect
OpenChip
Limerick, IrelandRISC-VVerificationSoC / ASICAug 30, 2026The Role: As a CPU Architecture Staff Engineer, you will be leading the architectural & micro-architectural specification for a range of cutting-edge OOO superscalar CPU cores used in next-generation System-on-Chip (SoC) designs, with a st
Senior CPU Architect
OpenChip
Limerick, IrelandRISC-VVerificationSoC / ASICAug 30, 2026The role: As a CPU Senior Architecture Engineer, you will be involved in the architectural & micro-architectural specification for a range of cutting-edge OOO superscalar CPU cores used in next-generation System-on-Chip (SoC) designs, with
- Roma, ItalyRTL / HDLVerificationFirmwareAug 30, 2026
The Role: As a Senior Functional Verification Engineer, you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work may
- Roma, ItalyRTL / HDLVerificationFirmwareAug 30, 2026
The Role: As a Functional Verification Principal Engineer, you will be interfacing with architecture, de-sign, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Your work
Junior DFT Engineer
OpenChip
Barcelona, Barcelona/Catalunya/Espanya, SpainRISC-VRTL / HDLVerificationAug 30, 2026We are actively seeking a Junior DFT Engineer to join our dynamic and growing Digital design team. The Role: • Work on design execution of silicon design • Work on SoC DFT architecture and DFM concept • Work on implementation and verifica
- Barcelona, Barcelona/Catalunya/Espanya, SpainRISC-VRTL / HDLVerificationAug 30, 2026
About Openchip Openchip is a European Silicon Engineering Company, headquartered in Barcelona, Spain. We aim to democratize the usage of Chips by developing Systems on Chip, SOCs, that combines RISC-V and accelerated chiplets for AI and HP