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Senior AI and Quant DevTech Engineer

NVIDIA Corporation

US, CA, Santa Clara, US, NY, New YorkCompilersPosted Aug 5, 2026
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Skills named in this posting

  • C
  • C++
  • CUDA
We are looking for a software engineer with a strong background in parallel processing and GPU architecture to push the limits of performance at the intersection of AI, high-performance computing, and financial markets. In this role, you will dive deep into parallel algorithms, GPUs, and sophisticated systems, identifying and eliminating bottlenecks to unlock the full power of the world’s most advanced processing hardware. You will collaborate with top experts across industry and academia, influence next-generation platforms, and share your insights with the global developer community. Do you enjoy solving hard technical problems, love performance tuning, and want your work to have a visible impact across an entire industry? If so, we'd love for you to consider this role. What you will be doing: • Designing and developing groundbreaking techniques to accelerate high-performance workloads at the intersection of AI, math, and financial systems. • Working hands-on with leading technical experts to analyze, optimize, and scale complex AI and HPC workloads for modern CPU and GPU architectures. • Profiling and eliminating performance bottlenecks across the stack—from algorithms to kernels to system-level behavior. • Publishing and presenting your work in conferences, talks, and blogs to educate and inspire the broader developer community. • Influencing the design of future hardware architectures, system software, libraries, and programming models by collaborating closely with NVIDIA research, hardware, compiler, and tools teams. What we need to see:  • Strong hands-on experience with CUDA and parallel programming. • Deep understanding of CPU/GPU architecture fundamentals and how they impact performance. • A Master’s or PhD in Computer Science, Computer Engineering, Electrical and Computer Engineering, or a related field. • Fluency in C/C++ and a solid foundation in algorithms and software design. • 5+ years of relevant work or research experience. • Proven experience improving the performance of large-scale computational applications on GPUs. • Excellent understanding of linear algebra. • Strong communication and organizational skills, with a logical approach to problem-solving and solid prioritization abilities. Ways to stand out from the crowd: • Experience with inference optimization techniques and deploying optimized AI models in production. • Experience with TensorRT, TensorRT-LLM, and cuTile. • Experience parallelizing and optimizing machine learning methods such as decision trees, time-series models, and Monte Carlo simulations. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 152,000 USD - 241,500 USD for Level 3, and 184,000 USD - 287,500 USD for Level 4. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until August 9, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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Original posting: jobs.nvidia.com

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RISC-V ecosystem

NVIDIA Corporation in the RISC-V ecosystem

RISC-V International: Premier Board

Founded in 1993, NVIDIA is an AI computing company. The company is headquartered in Santa Clara, California.

  • NVIDIA is bringing CUDA platform support to RISC-V, i.e. allowing a RISC-V CPU to host CUDA GPU applications
  • Publicly credited the RVA23 profile as the enabler: "We wouldn't have considered porting CUDA to RISC-V without it"
  • Active in RISC-V International profile/standards work and a frequent presence in RISC-V ecosystem coverage

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