SoC Chip Design Engineer for DFT/DFM
Overview
The successful candidate will be responsible for DFT and DFM methodologies, design, and implementation for our advanced automotive system-on-chip (SoC) designs.
The candidate will also collaborate with the design and layout teams to integrate DFT/DFM requirements.
• SoC testing architecture design
• Support project NPI(new product introduction) to MP(mass production) (test program development, coverage enhancement, yield improvement, cost reduction)
• Cowork w/ IP, test engineer, process team, board design to fulfill CP/FT/SLT test requirement.
#LI-JK1
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Original posting: careers.mediatek.com
RISC-V ecosystem
MediaTek Inc in the RISC-V ecosystem
RISC-V International: Strategic
We make semiconductor technology for #Smartphone, #IoT, #Network as well as TV, Tablet, Blu-ray & many other devices.
- Named in coverage of RISE, the Linux Foundation Europe RISC-V Software Ecosystem project, and RISC-V edge-AI market analysis
- Listed on the landscape as a RISC-V International member
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