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Lead Software Engineer - Liberate

Cadence Design Systems, Inc.

SHANGHAIRTL / HDLPhysical designPosted Sep 21, 2026
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Cadence Design Systems, Inc.
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Skills named in this posting

  • Verilog
  • VHDL
  • STA
  • C++
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The candidates should have two or more years of experiences in developing EDA software.  Must be proficient in C, C++, TCL, and development in Linux/Unix.  Knowledge on semiconductor device is strong plus.  Experience with SPICE or SPICE-like circuit simulation is important.  Knowledge of Verilog and VHDL is also highly desirable.  Have a good understanding of library characterization, IP design, static timing analysis, power analysis, and signal integrity analysis flows.  Minimum Education Required / Minimum Experience Required : MS, EE, CS, Math or Physics 2  Preferred Education / Preferred Experience: Ph.D. , EE, CS, Math or Physics 3-5 We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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