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Formal Verification Internship

Synopsys

Bengaluru, IndiaRTL / HDLVerificationPosted Oct 21, 2026
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Overview

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Skills named in this posting

  • SystemVerilog
  • Verilog
  • Formal verification
  • SVA
  • Python
  • Tcl
  • Perl
Date posted 10/20/2026 Category Interns/Temp Hire Type Intern Job ID 19193 Remote Eligible No Date Posted 10/20/2026 We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world. Internship Experience: At Synopsys, Interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today! Mission Statement: Our mission is to fuel today’s innovations and spark tomorrow’s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive—both at work and beyond. What You’ll Be Doing: �� Learn the latest formal verification methodology from experts and apply your learnings to live projects. • Work with a team of seasoned FV engineers and execute validation as per defined plans. • Support quality improvements and contribute insights that help enhance verification tool capabilities. What You’ll Need: • Currently pursuing a B.E./B.Tech/M.Tech in Electronics, Electrical, Instrumentation, or related fields (Candidates graduating 2027 will be preferred). • Strong academic foundation with relevant coursework, projects, or internships in semiconductor design. • Strong knowledge of computer architecture and digital design fundamentals. Exposure to the domains of Formal Verification, Verilog/SystemVerilog design, System Verilog Assertions is a plus. • Excellent problem-solving skills and analytical thinking abilities. • Strong communication and collaboration skills to work effectively in team environments. • Proficiency in scripting languages (Python, Perl, Tcl) within Unix/Linux environments. Key Program Facts: • Program Length: 12 Months Internship Program • Location: Bengaluru, India • Working Model: In-office • Full-Time/Part-Time: Full-Time • Start Date: Oct/ Nov 2026 Equal Opportunity Statement: Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Original posting: careers.synopsys.com

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RISC-V ecosystem

Synopsys in the RISC-V ecosystem

Synopsys makes chip design software and processor IP, including ARC-V RISC-V cores. It acquired Intrinsic ID in 2024.

  • Security-IP (PUF/authentication) supplier active in the RISC-V ecosystem, incl. RISC-V Foundation showcases at Embedded World
  • Associated with RISC-V side-channel mitigation research (XDIVINSA instruction diversification)

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