Staff ASIC Design Engineer

**Job Title** Staff ASIC Design Engineer - Agentic Workflows **About Cognichip** At Cognichip, we are building AI-native tools that transform how semiconductor engineers create, verify, and optimize chips. Our platform combines large proprietary models, agentic workflows, domain-specific engineering intelligence, and high-performance simulation infrastructure to accelerate one of the world's most complex engineering disciplines. **About the Role** We are seeking a Staff ASIC Design Engineer who will not just design chips, but will create the libraries, IP, benchmarks, and agent-ready knowledge that teach our AI how to design chips. This role sits at the heart of what makes Cognichip different. The semiconductor industry has run the same design playbook for forty years. We are changing that by encoding deep silicon expertise directly into AI models and autonomous workflows. The person in this role will be the domain authority who makes that possible, translating hard-won chip design knowledge into the training data, benchmarks, and structured processes that power our platform. If you want your expertise to outlast any single tape-out and instead shape how an entire industry designs silicon, this is that opportunity. **Key Responsibilities** - Encode your expert chip design knowledge including RTL/DV best practices, microarchitectural patterns, and EDA tool usage directly into AI models that drive design process autonomously - Develop high-quality RTL libraries, IP blocks, and processor designs that serve as training data and composable components within our design environment - Design end-to-end workflows for chip design, verification, and debugging with clear inputs, outputs, and success criteria - Generate and curate large-scale datasets of syntactic and semantic hardware code to improve model robustness and design quality - Build and maintain benchmarks and reference designs that evaluate and accelerate the performance of our AI tooling - Collaborate closely with ML researchers and software engineers, serving as the primary hardware domain expert who translates silicon constraints into actionable model training and agentic design insights **Required Qualifications** - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related field - 10 to 12+ years of experience in RTL design, verification, or both across digital IC, ASIC, or SoC - Strong hands-on expertise in SystemVerilog, RTL, lint, CDC/RDC, STA, and microarchitecture - Experience with Xilinx/AMD or Intel/Altera ecosystems, or ASIC physical design chains including SoC and IP integration - Familiarity with industry-standard protocols such as PCIe, CXL, DDR5, and NoC - Proficiency in Python for design automation and tool integration - Strong written and verbal communication skills, with the ability to bridge chip design and AI/software teams **Preferred Qualifications** - The following are not required but are great bonuses: - Experience with LLM-based agent systems, ML models, prompt engineering, or workflow decomposition - Familiarity with agent orchestration frameworks such as LangGraph, LangChain, or AutoGen - Experience with open-source EDA tools such as Verilator, CocoTB, Yosys, or OpenSTA - Demonstrated coursework or project experience in machine learning or deep learning - Personal projects showcasing innovation, continuous learning, or open-source contribution **What It's Like Here** - We are a fast-moving AI startup with a collaborative, high-trust culture - We value technical excellence, ownership, and the freedom to experiment - Our best work happens when builders and innovators work closely together to turn ambitious ideas into category-defining products - We operate on a hybrid schedule with four days in office, one day remote - If you are excited to build cutting-edge tools that empower semiconductor engineers and reshape how chips are designed, you will feel right at home.