Director - STA

Business Line Description: AI and Chip Engineering SoC Implementation team is seeking a passionate technologist who thrives in solving complex problems for the role of Static Timing Design Manager. As STA Manager, you will be managing a team of motivated engineers working on the AI, Edge and Automotive Processors in NXP. You will be working on fast paced, and leading-edge advanced node technologies building exciting and complex SoCs. You will be a major influence in the development, and support of the SoC implementation organization’s charter to build world-class MPUs. Job Summary: Timing Analysis activities for MPU SoCs. • Expertise in developing, implementing and verifying STA constraints • Expertise in efficient closure of Subsystem as well as SoC-level timing • In-depth knowledge of industry standards and practices in Timing closure, Physical Design, Floor-planning, and Place & Route • Knowledge of basic Architecture and Verilog to collaborate with RTL and IP design teams for timing fixes • Contribute to timing flow and methodology improvements • Collaborate with members of a global design team to complete large SoC (system-on-chip) projects. Cross functional collaboration: • Partner with Architecture and RTL teams to influence early design decisions • Ability to coordinate with all aspects of SOC design functions, including RTL, DV, DFT, EDA vendors, DTCO while setting technical direction for the team • Work with methodology teams to continuously improve flows and processes Key Challenges: • Demonstrate strong expertise in all aspects of timing analysis for a wide variety of designs, from constraint generation and verification to full-chip timing closure across all modes and scenarios. • Deep understanding of advanced topics such as crosstalk, noise, OCV, timing margins. Familiarity with Clock specs, jitter, IR drop, spice analysis. • Experience working with multi-site teams for execution is a must Job Qualifications: • BS or MS in Electrical or Computer Engineering • 15+ years of experience in Physical Design for complex SoCs • Experience with at least 3 years of STA Lead roles • Excellent communication skills, both oral and written • Innovate and adapt to the rapid use of AI and agents in STA & PD domains More information about NXP in the United States... NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals. #LI-6692