DFT DV Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: The S3 DFT team fully own AMD S3BU (Strategic Silicon Solution Business Unit) SOC DFT definition, Implementation, verification till final silicon bring up. We design the APUs mainly for consoles. Design Verification team is part of the whole chip design team and responsible to make sure the RTL quality. You will be working with DFT design and front-end team to verify the debug logic and make sure it is working on post-Si. THE PERSON: • Has related knowledge for design verification and good debug skills. • Familiar with entire ASIC design flow • Has good communication skills and be able to work both independently and in a team. • Should have strong problem-solving skills KEY RESPONSIBILITIES: Qualified candidate will perform some or all functions below: • Develop test plan according to the specification and review with Architect and Designer. • Develop test scenarios to verify the design and analyze the coverage. • Complete the verification task before TO. • Participate in ATE bring-up and debug the DFT patterns on ATE. PREFERRED EXPERIENCE: • Proficient in one kind of simulation tool like VCS, have good debug skill. • Familiar with SystemVerilog/C/C++ language. • Have the knowledge for UVM. • Familiar with script language like SHELL/Perl/Python. • It is better to have the DFT related knowledge like IEEE1149.1/6 for JTAG/BSCAN • Have Memory BIST knowledge is a plus. • Have background knowledge of High-Speed IO(USB/PCIE/DDR/Display) is a plus. • Familiar with the whole verification flow from test plan review to TO. • Have experience for post-Si debug is a plus. • Good written and spoken English ACADEMIC CREDENTIALS: • Bachelor or Master, major in EE, CS or related area 8+ years working experience. LOCATION: • Shanghai, Beijing #LI-VC1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. THE ROLE: The S3 DFT team fully own AMD S3BU (Strategic Silicon Solution Business Unit) SOC DFT definition, Implementation, verification till final silicon bring up. We design the APUs mainly for consoles. Design Verification team is part of the whole chip design team and responsible to make sure the RTL quality. You will be working with DFT design and front-end team to verify the debug logic and make sure it is working on post-Si. THE PERSON: • Has related knowledge for design verification and good debug skills. • Familiar with entire ASIC design flow • Has good communication skills and be able to work both independently and in a team. • Should have strong problem-solving skills KEY RESPONSIBILITIES: Qualified candidate will perform some or all functions below: • Develop test plan according to the specification and review with Architect and Designer. • Develop test scenarios to verify the design and analyze the coverage. • Complete the verification task before TO. • Participate in ATE bring-up and debug the DFT patterns on ATE. PREFERRED EXPERIENCE: • Proficient in one kind of simulation tool like VCS, have good debug skill. • Familiar with SystemVerilog/C/C++ language. • Have the knowledge for UVM. • Familiar with script language like SHELL/Perl/Python. • It is better to have the DFT related knowledge like IEEE1149.1/6 for JTAG/BSCAN • Have Memory BIST knowledge is a plus. • Have background knowledge of High-Speed IO(USB/PCIE/DDR/Display) is a plus. • Familiar with the whole verification flow from test plan review to TO. • Have experience for post-Si debug is a plus. • Good written and spoken English ACADEMIC CREDENTIALS: • Bachelor or Master, major in EE, CS or related area 8+ years working experience. LOCATION: • Shanghai, Beijing #LI-VC1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.