MTS, Static Timing Analysis (STA) Lead (AI2555)

Description Job Title: MTS, Static Timing Analysis (STA) Lead Job Location: Bangalore, India (This position requires a full-time, on-site presence in our Bangalore, India Office) Job ID: AI2555 Job Description: We are seeking a high-caliber Static Timing Analysis (STA) Lead to spearhead chip-level timing signoff and drive closure strategies for next-generation, high-performance ML-SoCs. In this role, you will take technical ownership of end-to-end timing closure across advanced process nodes (7nm, 5nm, and below), establishing methodologies that bridge early synthesis through final GDSII tapeout. You will work closely with cross-functional architecture, RTL, Physical Design, DFT teams to solve complex timing and power challenges under aggressive schedules. As a technical lead, you will shape full-chip timing strategy, optimize power-performance-area (PPA) trade-offs, and mentor engineering talent to deliver first-pass silicon success. Role & responsibilities: • End-to-End Timing Strategy & Signoff: Define and execute the full-chip and block-level STA signoff strategy across multi-corner, multi-mode (MMMC) conditions, spanning synthesis, placement, clock tree synthesis (CTS), and signoff. • Constraints Understanding: Understand SDC constraints (including complex generated clocks, multi-cycle paths, false paths, IO timing, and mode switching) to ensure alignment with design intent and flag constraints issues to RTL & DFT teams. • Analysis & Debug: Lead complex timing debug sessions addressing setup, hold, signal integrity (SI), crosstalk, noise, and recovery/removal checks across all operational modes and PVT (process, voltage, temperature) corners. • Advanced Effects Mitigation: Apply and fine-tune variation methodologies (AOCV, POCV/SOCV), parasitic extraction correlation, and derating factors to balance signoff margins without unnecessary pessimism. • ECO Implementation & Power Correlation: Drive functional and timing ECO loops (automated and manual). Run timing/power signoff analysis (PrimePower/PT-PX) to evaluate the power impact of timing fixes. • Clocking & Partitioning: Partner with backend teams to refine clock distribution networks, evaluate power-optimized clock gating, and develop quality timing models/methodologies for hierarchical timing closure. • Automation & Flow Innovation: Architect and extend infrastructure using TCL, Python, and Perl scripts to streamline timing reporting, automate regression suites, and explore AI/ML-driven closure techniques. • Cross-Team Leadership: Serve as the central point of contact for timing convergence, aligning RTL, DFT, synthesis, physical design workflows while providing technical mentorship to team members. Minimum Requirements: • Bachelor’s or Master’s degree in Electrical/Electronics/Microelectronics/Computer Engineering, or a related technical discipline. • 12+ years of hands-on experience in STA, timing closure, and physical design workflows, with proven lead experience on complex SoC tapeouts in sub-7nm process nodes. • Tool Expertise: Industry-standard mastery of Synopsys PrimeTime (PrimeTime-SI, PT-PX, PrimeClosure/Tweaker) which is preferred or Cadence Tempus. • Core Technical Knowledge: • Deep understanding of timing signoff flow, development and deployment of the same. • In-depth expertise in interface timing closure without block re-spin and deploying strategies that enable block internal and block/SoC interface timing closure. • Strong understanding of physical design fundamentals (Placement, CTS, Routing, Netlist-to-GDS). • In-depth knowledge of physical effects (parasitics, StarRC correlation, IR drop impact on timing, SI/crosstalk). • Advanced proficiency in TCL scripting (required) alongside Python or Perl (preferred). Preferred Qualifications: • Direct experience managing joint STA and Physical Design combined closure ownership. • Background in multi-mode timing closure of multi-million gate count SoC having >20 blocks and sub-systems. • Experience integrating advanced ECO automation engines and applying machine learning utilities to timing analysis. • Demonstrated track record of leading cross-functional engineering teams through critical project milestones. Leadership Profile & Mindset • Technical Ownership: High accountability with the ability to navigate ambiguous, complex timing issues and deliver systematic solutions. • Strategic Collaboration: Excellent communication skills with a track record of driving consensus across global design, verification, and implementation teams. Continuous Improvement: Passionate about innovating internal workflows, adopting industry advancements, and helping team members elevate their technical skills. Personal Attributes: Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.