Senior Chip Design Engineer
Overview
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We are now looking for a Senior Chip Design Engineer for the Switch Silicon group.
As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation pioneering Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
What you'll be doing:
• Work in a combined design and verification team which develops some of the switch silicon core units.
• Build reference models, verify and simulate chip blocks/entities according to specifications.
• Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.
What we need to see:
• Proven experience in RTL design or RTL verification.
• 4+ years of relevant experience.
• Previous experience in networking - an advantage.
• B.Sc. in Electrical Engineering or Computer Engineering, or equivalent experience.
• A great teammate with good communication and social skills.
NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come, join our Switch Silicon design team and help us build the next chip in this exciting and quickly growing field.
Apply on the employer's site
Original posting: jobs.nvidia.com
RISC-V ecosystem
NVIDIA Corporation in the RISC-V ecosystem
RISC-V International: Premier Board
Founded in 1993, NVIDIA is an AI computing company. The company is headquartered in Santa Clara, California.
- NVIDIA is bringing CUDA platform support to RISC-V, i.e. allowing a RISC-V CPU to host CUDA GPU applications
- Publicly credited the RVA23 profile as the enabler: "We wouldn't have considered porting CUDA to RISC-V without it"
- Active in RISC-V International profile/standards work and a frequent presence in RISC-V ecosystem coverage
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