Software Engineer II
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- Place and route
- C
- C++
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Placement Team (Cadence Innovus)
Job Description
As a member of our Placement Team, you will design, develop, maintain, and enhance our cutting-edge detailed placement technologies. You will work at the forefront of advanced semiconductor design, developing lithography-driven placement solutions for leading-edge process nodes.
The primary responsibility of this role is to design, develop, troubleshoot, and debug software applications on Unix/Linux platforms.
Core Responsibilities
• Lead the development and maintenance of core placement algorithms.
• Design, implement, and enhance advanced placement technologies and methodologies.
• Collaborate with the Routing and OPT teams to define and develop next-generation algorithms.
• Conduct peer code reviews and maintain high standards for code quality, scalability, thread safety, and test coverage.
• Work closely with cross-functional teams to improve solution quality, performance, and usability.
Requirements
• Strong software development skills in C/C++.
• Solid understanding of QoR (Quality of Results) and PPA (Performance, Power, and Area) optimization.
• Proven experience with EDA back-end design flows, including placement, timing analysis, optimization, and routing.
• Strong interest in and understanding of developing complex software systems on Unix/Linux platforms.
• Excellent verbal and written communication and presentation skills.
• Experience working with TSMC and semiconductor design companies is a strong plus.
• M.S. degree in Electrical Engineering, Computer Science, or a related field required; Ph.D. preferred.
We’re doing work that matters. Help us solve what others can’t.
Apply on the employer's site
Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
Same employer
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