Performance Modeling and Optimization Engineering Director

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Performance Modeling and Optimization Engineering Director: THE ROLE The Director is responsible for owning end to end silicon (i.e., pre – post silicon) performance and design execution. This role provides technical and organizational leadership for system-level performance attainment, hardware/software optimizations, silicon debug, and sustained performance delivery for complex SoCs and accelerators. The Director drives cross functional alignment across architecture, modeling, design, validation, software, and product teams to ensure performance, power, and efficiency targets are met for current and future products. THE PERSON In this role you would manage a global organization of ~30+ engineers, with growth potential to 50+. Direct impact on product competitiveness, customer performance outcomes, and long-term silicon roadmap success. KEY RESPONSIBILITIES Technical Leadership • Own system level performance attainment and HW/SW optimization to improve out of box and sustained performance across silicon products. • Lead post-silicon debug, regression, performance analysis, and optimization efforts to achieve committed product targets. • Establish and evolve methodologies for power and performance modeling, validation, and silicon bring up. Execution & Delivery • Lead execution across multiple silicon programs, ensuring performance and power goals are met on schedule. • Partner closely with architecture, RTL design, verification, firmware, system software, and product management teams. • Identify and mitigate technical and execution risks across the silicon lifecycle. • Drive continuous improvement in tools, flows, and best practices for silicon design and performance engineering. People & Organizational Leadership • Build, scale, and lead a global team of silicon design and performance engineers. • Manage senior technical leaders (Fellows, Senior Fellows, Directors) and develop succession plans. • Set clear technical direction, performance expectations, and career development paths for the organization. • Foster a culture of technical excellence, accountability, and collaboration. Cross Functional & External Engagement • Serve as a primary technical interface with internal senior leadership, including Directors, Senior Directors, Fellows, and Engineering VPs. • Engage externally with customer platform engineering teams, engineering leads, and product stakeholders as needed. • Represent silicon design and performance perspectives in executive reviews and customer engagements. PREFERRED EXPERIENCE: • Extensive experience in silicon design engineering, performance architecture, or related technical domains. • Deep understanding of SoC architecture, performance modeling, power analysis, and silicon debug. • Proven experience leading large, global engineering teams. • Strong cross functional leadership and communication skills. • Demonstrated ability to drive complex technical programs from concept through post silicon execution. • Experience with high performance compute, AI accelerators, GPUs, or largescale SoCs. • Background in both hardware and system/software performance optimization. • Prior experience interfacing with external customers or partners on silicon performance topics. ACADEMIC CREDENTIALS:  • Bachelor’s or master’s degree in electrical or computer engineering #DC-GPU #LI-PK1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. Performance Modeling and Optimization Engineering Director: THE ROLE The Director is responsible for owning end to end silicon (i.e., pre – post silicon) performance and design execution. This role provides technical and organizational leadership for system-level performance attainment, hardware/software optimizations, silicon debug, and sustained performance delivery for complex SoCs and accelerators. The Director drives cross functional alignment across architecture, modeling, design, validation, software, and product teams to ensure performance, power, and efficiency targets are met for current and future products. THE PERSON In this role you would manage a global organization of ~30+ engineers, with growth potential to 50+. Direct impact on product competitiveness, customer performance outcomes, and long-term silicon roadmap success. KEY RESPONSIBILITIES Technical Leadership • Own system level performance attainment and HW/SW optimization to improve out of box and sustained performance across silicon products. • Lead post-silicon debug, regression, performance analysis, and optimization efforts to achieve committed product targets. • Establish and evolve methodologies for power and performance modeling, validation, and silicon bring up. Execution & Delivery • Lead execution across multiple silicon programs, ensuring performance and power goals are met on schedule. • Partner closely with architecture, RTL design, verification, firmware, system software, and product management teams. • Identify and mitigate technical and execution risks across the silicon lifecycle. • Drive continuous improvement in tools, flows, and best practices for silicon design and performance engineering. People & Organizational Leadership • Build, scale, and lead a global team of silicon design and performance engineers. • Manage senior technical leaders (Fellows, Senior Fellows, Directors) and develop succession plans. • Set clear technical direction, performance expectations, and career development paths for the organization. • Foster a culture of technical excellence, accountability, and collaboration. Cross Functional & External Engagement • Serve as a primary technical interface with internal senior leadership, including Directors, Senior Directors, Fellows, and Engineering VPs. • Engage externally with customer platform engineering teams, engineering leads, and product stakeholders as needed. • Represent silicon design and performance perspectives in executive reviews and customer engagements. PREFERRED EXPERIENCE: • Extensive experience in silicon design engineering, performance architecture, or related technical domains. • Deep understanding of SoC architecture, performance modeling, power analysis, and silicon debug. • Proven experience leading large, global engineering teams. • Strong cross functional leadership and communication skills. • Demonstrated ability to drive complex technical programs from concept through post silicon execution. • Experience with high performance compute, AI accelerators, GPUs, or largescale SoCs. • Background in both hardware and system/software performance optimization. • Prior experience interfacing with external customers or partners on silicon performance topics. ACADEMIC CREDENTIALS:  • Bachelor’s or master’s degree in electrical or computer engineering #DC-GPU #LI-PK1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.