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EDA PV Intern for Digital Backend Flow

Cadence Design Systems, Inc.

SHANGHAIPhysical designPosted Sep 21, 2026
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Cadence Design Systems, Inc.
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Skills named in this posting

  • Place and route
  • Python
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities: a) Assist in Cadence P&R tool Innovus's regression review b) Develop and maintain system and infrastructure for high productivity and efficiency with various scripting and system development techniques. Requirements: • Master in EE or CS • IC design knowledge is necessary, statistic timing analysis knowledge or physical knowledge is a strong plus • Unix System knowledge, tclsh/cshell/perl/python and other scripting skill will be plus • Good communication in English and Chinese, good confidence and good self-motivation. • Commitment to work as intern at least 4 days per week for more than 6 months We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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