Graduate Digital Design Engineer

Description About the Business Unit Ceva is at the forefront of next-generation cellular communication systems. We build licensable 5G modem IP for User Equipment (UE) and base stations, from IoT-class devices to high-throughput infrastructure. Our platforms target the latest 5G-Advanced releases. A fast-growing focus is space and satellite infrastructure: 5G satellite networks that bring standard cellular connectivity to LEO/GEO satellites and direct-to-device links. This domain brings unique challenges, including large Doppler shifts, long round-trip delays, radiation-aware design and tight power budgets. About the Role As a Digital Design Engineer, you'll join the team that designs the DSP cores and baseband hardware accelerators behind our next-generation modem products. Working alongside senior designers, you'll take on well-defined blocks and grow into the full design flow, from specification and RTL to synthesis and timing. It's a hands-on role with close collaboration across algorithms, architecture, verification and backend teams, and a strong place to build a career in VLSI design. What You'll Do Write and debug RTL (Verilog/SystemVerilog) for blocks within 5G baseband DSP cores and hardware accelerators, under the guidance of senior engineers. Translate block-level specifications into clean, well-documented, synthesizable designs. Run lint, synthesis and timing analysis on your blocks, and help resolve the issues they raise. Support verification engineers in bringing up testbenches, debugging failures and reaching coverage goals. Take part in design reviews and learn to weigh power, performance and area (PPA) trade-offs. Work with algorithm, verification and backend teams to understand how your blocks fit into the full modem. Requirements • B.Sc. in Electrical or Computer Engineering (recent graduates) • An experience in digital or VLSI design from student projects or internships. • Solid grasp of digital design fundamentals: logic design, FSMs, pipelining, clocking and timing • Basic familiarity with simulation and EDA tools (Synopsys, Cadence, Siemens EDA/Mentor or similar) • Eagerness to learn, good problem-solving skills and clear communication in English Advantages • Hands-on RTL design in Verilog or SystemVerilog, from academic or industry projects • M.Sc. in Electrical Engineering • Coursework or projects in signal processing or digital communication systems • Scripting skills (Python, Tcl or Perl) for design automation