Lead Education Application Engineer (RF/Microwave)
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- Mixed-signal
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Summary:
• As part of the Cadence Customer Education Team, you will create and deploy customer training across various platforms for Cadence's state-of-the-art tools, languages, and methodologies. The training content you develop will be used globally for classroom, online, and virtual delivery.
Job responsibilities:
• Work with Cadence product engineers, R&D, application engineers, product marketing, and our in-house instructional design team to create training materials that are focused, relevant, and highlight the product’s latest features and methodologies.
• Develop and update course lectures, labs, and related collateral to enable our customers to become highly productive with Cadence tools in the shortest possible time.
• Create narrated online videos and demos, providing customers with snippets on Cadence tools, languages, and methodologies
Experience and Technical Skills required
• Excellent written and verbal English communication skills.
• Engineering Degree with a background in analog/RF/microwave design. RFIC and package design is a plus.
• Well-versed with the complete front-back analog IC design flow.
• Knows design, layout constraints, extraction, and packaging constraints.
• Knowledge of EMI in analog/RF and has possibly run EM simulations.
• Has worked within the Cadence Virtuoso environment and used the Spectre Circuit simulator.
• Used Cadence Microwave Office (AWR) and associated tools.
• Used or has knowledge of Cadence EMX/EMXDesigner tools.
• Is proficient with MS PowerPoint and MS Word.
• Enjoys a mixture of activities – authoring content, learning new tools and methodologies, “being the expert,” teaching and interacting with customers, and working with highly competent and experienced engineers
• Process-oriented, quick to learn, and can multi-task efficiently.
• Given clear goals, can work independently to accomplish such goals
The ideal candidate:
• Has strong written and verbal English communication skills.
• Enjoys various activities – authoring content, learning new tools and methodologies, “being the expert,” teaching and interacting with customers, and working with highly competent and experienced engineers.
• Given clear goals, can work independently to accomplish such goals.
• Is aware of analog/mixed-signal design, simulation, layout, and verification flows/methodologies.
• Extensive IC layout experience in analog/mixed‑signal domains, covering designs from simple to highly complex (AA), with thorough handling of all corner cases (PVT variations and mismatch).
• Demonstrated ability to deliver robust layouts that meet stringent performance and reliability targets.
• Strong knowledge of the complete physical design and sign-off flow, including layout verification (DRC/LVS), parasitic RC extraction (PEX), post-layout simulation, EM/IR (EMIR) analysis, reliability checks (ESD, LUP), and seamless integration through tape‑out.
• Has working knowledge of Cadence design tools such as Virtuoso, Pegasus, PVS, Quantus, and the SKILL IDE.
• A plus is having CAD experience and having worked on PDK development/PDK Cockpit
• Should have a Bachelor’s or Master's degree in Electrical/Electronics Engineering with a minimum 4-6 years of related working experience.
Be proud and passionate about the work you do. Together, our One Cadence -- One Team culture drives our success.
We’re doing work that matters. Help us solve what others can’t.
Apply on the employer's site
Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
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