Sr Principal Software Engineer
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- Verilog
- VHDL
- STA
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Position: Sr. Principal Software Engineer
Grade: T5
Experience: 12- 16 Years
Location: Bangalore/Noida
Job Responsibilities:
R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power.
This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out!
Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills.
Job Qualifications:
BE/BTech/ME/MTech- Computer Science or others
Required Skills
The candidate should have hands-on experience in RTL Coding. The candidate should be able to
• write, update, and optimize register-transfer level code using System Design Guide standards in VHDL or Verilog.
• run functional simulations (using Xcelium), static timing analysis, and design-for-test checks to find bugs.
• validate, test, and investigate performance/accuracy issues in the simulator.
Knowledge of Design-For-Test (DFT) and/or Memory-Built-In-Self-Test (MBIST) is a plus.
We’re doing work that matters. Help us solve what others can’t.
Apply on the employer's site
Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
Same employer
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