G7 Fellow – High-Speed Interfaces & Clocking Strategy
Overview
Skills named in this posting
- UCIe / chiplets
- SerDes
Key ResponsibilitiesTechnology Strategy & Roadmap Leadership
• Define and drive NXP’s long-term strategy for high-speed interfaces, clocking architectures, PLL technologies, and associated analog foundation IP.
• Analyze current and future requirements across all NXP Business Lines and Product Lines.
• Develop technology roadmaps aligned with market trends, customer needs, and product strategies.
• Identify opportunities for technology consolidation, platform reuse, and architectural alignment across NXP.
• Establish strategic priorities and investment recommendations to strengthen NXP’s competitive position.Portfolio Analysis & Make-or-Buy Decisions
• Assess NXP’s portfolio requirements across automotive, industrial, secure connected edge, networking, and computing applications.
• Evaluate internal capabilities, external IP offerings, partnerships, and acquisition opportunities.
• Develop and recommend make-versus-buy strategies for PHYs, SerDes, clocking, PLL, and related technologies.
• Provide strategic guidance on technology investments based on technical differentiation, reuse potential, time-to-market, and business impact.Clocking & PLL Technology Leadership
• Define company-wide clocking and synchronization strategies.
• Drive the roadmap for next-generation clock generation and PLL solutions with focus on:Low jitterLow powerSmall areaScalability across process nodesHigh-performance operationFunctional safety requirements
• Lead development of architectural frameworks for clock distribution, synchronization, timing integrity, and system-level clock management.High-Speed Interface Architecture
• Provide technical leadership for connectivity technologies including:I3CUSB / eUSBEthernetUSXGMIIMIPIDDRPCIeCXLUCIeEmerging chiplet interconnect technologies
• Guide future PHY and SerDes architectures supporting multi-gigabit and chiplet-based systems.Innovation & Technical Excellence
• Establish and maintain a long-term innovation roadmap for high-speed interfaces and clocking technologies.
• Anticipate emerging industry trends and identify opportunities for NXP differentiation.
• Drive benchmarking, technology assessments, and architectural studies.
• Foster technical excellence and innovation across engineering communities.
• Represent NXP in strategic technical discussions with customers, partners, standards bodies, and ecosystem leaders.
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Original posting: nxp.wd3.myworkdayjobs.com
RISC-V ecosystem
NXP Semiconductors Netherlands B.V. in the RISC-V ecosystem
RISC-V International: Strategic
NXP Semiconductors NV is American Dutch semiconductor manufacturer with dual headquarters in Eindhoven, Netherlands and Austin, Texas.
- NXP is putting RISC-V cores into its mainstream products: a Linux-capable RISC-V core was reported to debut on an NXP i.MX SoC
- Broad MCU/applications-processor vendor tracked in RISC-V market analyses alongside other incumbents
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