Power Analysis and Optimization Engineer - New College Graduate 2027
Overview
- Added in 30 days
- 647
- At this company, still open
Skills named in this posting
- STA
- Place and route
- Low-power design (UPF)
- C++
- Python
- Tcl
NVIDIA is committed not only to delivering outstanding chip performance but also to continuously improving power efficiency across every product. Performance per watt is critical to our success.
The Power Analysis and Optimization team works closely with architecture, design, verification, and physical-design teams to define power targets for architectural changes and new features. We identify power-saving opportunities throughout the ASIC design process—from architecture definition through place and route—and resolve power issues that could affect functionality or performance.
Joining the team, you will contribute to ASIC power analysis, modeling, optimization, and flow automation. Your work will help make NVIDIA GPU and SoC products more energy-efficient and maintain their leadership in performance per watt.
What you’ll be doing
• Develop IP-level power models to estimate the impact of architectural changes and new features.
• Analyze power consumption across different workloads and application scenarios.
• Collaborate with architects and design teams to define power targets and evaluate power, performance, and area tradeoffs.
• Use internally developed flows and industry-standard tools to identify power inefficiencies and optimization opportunities.
• Work with RTL and physical-design teams to implement and validate power optimizations.
• Investigate power regressions and determine their architectural, RTL, workload, or physical-design root causes.
• Develop scripts, automation flows, and AI-assisted solutions to improve the efficiency and scalability of power analysis.
• Explore new methodologies for power modeling, analysis, attribution, and optimization.
What we need to see
• Expected to graduate in 2027 with a MS or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Strong understanding of digital circuit design, computer architecture, or ASIC design methodology.
• Understanding of power-consumption fundamentals and common low-power design techniques.
• Programming or scripting experience in Python, C++, Tcl, or a similar language.
• Good written and verbal communication skills in English.
Ways to stand out from the crowd
• Familiarity with ASIC power-analysis tools such as PrimeTime PX or PowerArtist.
• Experience with power modeling, workload analysis, power attribution, or low-power design.
• Experience analyzing power, performance, and area tradeoffs.
• Experience developing or integrating AI agents, engineering skills, or AI-assisted automation workflows.
NVIDIA is widely considered one of the technology industry’s most desirable employers, bringing together some of the world’s most talented and innovative people. Are you creative, analytical, and eager to improve the power efficiency of cutting-edge GPU and SoC designs? Do you enjoy understanding complex architectures, analyzing power behavior, and finding opportunities to improve performance per watt? If so, we want to hear from you.
NVIDIA is committed to fostering a diverse work environment and is proud to be an equal opportunity employer. We highly value diversity among our current and future employees and do not discriminate—including in our hiring and promotion practices—on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.
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Original posting: jobs.nvidia.com
RISC-V ecosystem
NVIDIA Corporation in the RISC-V ecosystem
RISC-V International: Premier Board
Founded in 1993, NVIDIA is an AI computing company. The company is headquartered in Santa Clara, California.
- NVIDIA is bringing CUDA platform support to RISC-V, i.e. allowing a RISC-V CPU to host CUDA GPU applications
- Publicly credited the RVA23 profile as the enabler: "We wouldn't have considered porting CUDA to RISC-V without it"
- Active in RISC-V International profile/standards work and a frequent presence in RISC-V ecosystem coverage
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