[2027 Campus Hire] Design Verification Engineer

[What you will do] • Module/IP/SOC design verification. • Develop and review test plans. • Develop verification environment/testbench in Module/IP/SOC level. • Develop verification IP and reference model. • Implement test with randomization-based coverage driven verification methodology. • Implement functional and functional/code coverage closure. • Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC. • Low Power verification. • Formal verification. • Verification automation flow. #LI-WC1