Lead Software Engineer
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- SystemVerilog
- UVM
- Emulation
- Logic synthesis
- C
- C++
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The engineer will work with a global team to develop and maintain high-quality C/C++ software for hardware-software co-simulation, including compiler and runtime components for Transaction-Based Acceleration (TBA).
The role includes supporting existing features and developing new capabilities for TBA technology in next-generation Palladium and Protium emulation systems. The engineer will also work closely with field application engineers to build and deploy high-performance TBA solutions on Cadence emulation and prototyping platforms.
Position Requirements
· Bachelor’s or Master’s degree in Computer Science or a related field. Premier Institute is preferred.
· At least 5 years of software development experience in Linux and C/C++.
· Strong C/C++ programming skills with a good understanding of data structures, algorithms, and multi-threaded programming.
· Experience with System Verilog is a plus. Familiarity with UVM, SC/TLM, and debugging RTL on simulation or emulation platforms is preferred.
. Working knowledge of RTL logic synthesis is preferred.
· Strong problem-solving, written, and verbal communication skills, with attention to detail and the ability to work effectively with global teams.
. Strong debugging skill with innovative approach to reach to issue in system level environment
. For development using AI, Ability to fine tune the prompts to get the desired result and review the AI output .
We’re doing work that matters. Help us solve what others can’t.
Apply on the employer's site
Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
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