Datacenter Compute SoC Architect

Role Summary We are seeking a highly experienced and visionary Datacenter Compute SoC Architect to lead the definition, design, and optimization of our next-generation high-performance computing SoCs. In this critical role, you will be responsible for defining the system-on-chip architecture for scalable datacenter processors, balancing Power, Performance, and Area (PPA) constraints while meeting aggressive cloud-scale workloads. You will work cross-functionally with CPU/Compute core architects, IP designers, performance modeling teams, and software/firmware engineers to deliver world-class silicon that powers the future of cloud computing and AI infrastructure. Key Responsibilities • SoC Architecture Definition: Lead the architectural definition of next-generation datacenter Compute SoCs, including core/instance counts, cache hierarchies, coherent interconnects, and memory subsystems. • IP Selection & Integration: Define requirements and drive decisions for third-party and internal IPs (e.g., PCIe Gen 5/6, CXL, DDR5/HBM controllers, Network-on-Chip/NoC, and security enclaves). • PPA Optimization: Conduct rigorous Power, Performance, and Area (PPA) trade-off analysis to ensure the SoC meets strict datacenter efficiency and performance-per-watt targets. • Advanced Packaging Strategy: Collaborate with packaging teams on multi-die/chiplet-based architectures, die-to-die (D2D) interconnect protocols (e.g., UCIe), and advanced thermal solutions. • HW/SW Co-Design: Partner closely with firmware, OS, and cloud infrastructure software teams to ensure the hardware architecture optimally supports modern hypervisors, cloud-native workloads, and virtualization technologies. • Performance Modeling: Work with the performance modeling team to define use cases, guide the creation of C++/SystemC architectural models, and analyze simulation data to identify bottlenecks. • Technical Leadership: Write detailed architecture specifications and serve as the technical lead during the RTL implementation, verification, and silicon bring-up phases. #LI-JK1