Principal AE (STA - SignOff)
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- STA
- Place and route
- Low-power design (UPF)
- Python
- Perl
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are looking for a Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital Implementation and Signoff tools. The candidate will work closely with sales executives in supporting sales campaigns by delivering workshops, benchmarks, product demonstrations, methodology consultations and product support.
Position also involves:
• Presenting to customers the technical capabilities of Cadence Digital Implementation and Signoff tools and flows (Synthesis, Place and Route, Timing/Physical/Power Signoff).
• Recognizing opportunities for products at existing customers or potential customers, and working with account team to define and execute technical campaigns
• Support technical evaluations/benchmarks and drive the process to deliver Cadence solutions implementations
• Ongoing support and usage proliferation at existing customers (on/offsite)
• Working closely with R&D on tools and methodology improvements
• Create and contribute technical content for Cadence Online Support
• Travel as required (up to 20%)
The Position Requirements are…
• Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals and Static Timing Analysis is required
• Experience with ASIC digital implementation flows and tools is a plus
• Working knowledge of a scripting language TCL/Perl/Python
• Minimum BS-EE plus 8 to 10 year’s experience or MS-EE plus 6 to 8 year’s experience
• Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions
• Candidate should have strong customer-facing communication and problem solving skills
• Strong personal drive for continuous learning and expanding professional skill sets
• Strong verbal and written communication skills
The annual salary range for California (Other than San Jose) is $116,200 to $215,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
Apply on the employer's site
Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
Same employer
More roles at Cadence Design Systems, Inc.
Sr Systems Engineer
Cadence Design Systems, Inc.
SHANGHAICompilersKernel / LinuxOct 28, 2026Sr Systems Engineer
Cadence Design Systems, Inc.
SHANGHAICompilersKernel / LinuxOct 28, 2026Sr Credit & Collections Analyst
Cadence Design Systems, Inc.
SHANGHAIOct 28, 2026Sr Principal Project Manager - AE
Cadence Design Systems, Inc.
SHANGHAIRTL / HDLVerificationSoC / ASICOct 28, 2026IT -Staff Systems Engineer - VM
Cadence Design Systems, Inc.
SHANGHAI 07Oct 28, 2026Software Engineer II: Hardware Job Scheduler R&D
Cadence Design Systems, Inc.
BELO HORIZONTERTL / HDLPhysical designSoC / ASICOct 28, 2026