Senior SerDes Design Verification Engineer
Overview
Skills named in this posting
- UCIe / chiplets
- SerDes
1. SerDes design verification in I/O Chiplet to collaborate with analog/digital/algorithm design teams and system application team from prototype test chip to mass production.
2. Responsible for implementing test script or designing test firmware for SerDes Analog IP quailification and PHY performance validation
3. Responsible for establishing automatic test program and data analysis for SerDes Analog IP and PHY characterization and failure analysis.
Apply on the employer's site
Original posting: careers.mediatek.com
RISC-V ecosystem
MediaTek Inc in the RISC-V ecosystem
RISC-V International: Strategic
We make semiconductor technology for #Smartphone, #IoT, #Network as well as TV, Tablet, Blu-ray & many other devices.
- Named in coverage of RISE, the Linux Foundation Europe RISC-V Software Ecosystem project, and RISC-V edge-AI market analysis
- Listed on the landscape as a RISC-V International member
Same employer
More roles at MediaTek Inc
- CambourneSoC / ASICOct 27, 2026
- CambourneSoC / ASICOct 27, 2026
- HsinChuCompilersOct 27, 2026
专利工程师 MBJ20261029(工作地:北京)
MediaTek Inc
BeijingOct 27, 2026专利工程师MSZ20261028
MediaTek Inc
ShenzhenOct 27, 2026Product Marketing
MediaTek Inc
HsinChuOct 26, 2026