Hardware Security Architect

The SoC Security Architect defines and drives the hardware security architecture for SoCs across a range of end applications, with deep expertise in hardware security and HW/SW interaction. You will own & establish the vision for future generations of security hardware. Job Responsibilities: • Define SoC hardware security architecture and requirements, including HSM specification, secure boot/RoT concepts, and cryptographic IP integration strategies.(AES/SHA/PKA/PUF/PQC etc) • Translate security features into high-level HW/SW specifications and derive HW requirements to design a product • Lead threat modeling, risk assessments, and vulnerability analysis; translate into architectural mitigations and design constraints. • Architect HW/SW security boundaries and co-design flows for secure boot, firmware services, drivers, and runtime protection. • Define secure key storage/provisioning (eFUSE/OTP) and security-aware DFT/TEST strategies balancing coverage and attack resistance. • Collaborate with architecture, RTL, verification, DFT, PD, and software teams to embed security into implementation and validation flows. • Ensure compliance with cybersecurity standards (ISO 21434), optimize for PPA trade-offs, and drive system-level security validation. • Stay current on threats/standards and provide technical leadership through reviews and security guidance. Other Responsibilities: • Collaborate with cross-functional teams (Architecture, RTL Design, Verification, DFT, Physical Design, Firmware/Software, Systems, Quality, and Product/Customer teams) to align security, safety, test, and product requirements and to support customer discussions, audits, and security reviews. • Ensure security, safety, and system-level design compliance in architecture, adhering to relevant standards (e.g., ISO 26262, IEC 61508). Qualifications: • Bachelor's or Master's degree in Electrical/Electronic/Computer Engineering or a related field. • 10–15+ years of experience in SoC or MCU design with a strong focus on hardware security architecture and HW/SW interactions. • Strong understanding of SoC architecture, AMBA/AXI-class interconnects, memory subsystems, and how security policies are enforced across HW/SW boundaries. • Proven experience with threat modeling, risk assessment, security validation, and vulnerability analysis for SoC-based systems. • Hands-on background with RTL design, synthesis concepts, and EDA flows sufficient to review and guide secure implementation (even if not the primary RTL owner). • Excellent written and verbal communication skills for specifications, reviews, and stakeholder alignment. More information about NXP in the United States... NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals. #LI-6aa0