Lead Product Engineer: System Verification and Emulation
BELO HORIZONTERTL / HDLVerificationFPGAPosted Sep 29, 2026
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- SystemVerilog
- Verilog
- Emulation
- C
- C++
- Python
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence Design Systems Inc. is seeking a highly motivated Lead Product Engineer: System Verification and Emulation to join our team in Belo Horizonte, Brazil.
As a Lead Product Engineer: System Verification and Emulation, you will independently drive Palladium customer engagements, acting as a technical lead for deployment, adoption, and optimization of emulation-based verification flows. You will work closely with R&D teams to influence product direction, drive new feature enablement, and ensure real‑world customer requirements are reflected in Cadence solutions. The objective is to increase customer productivity by delivering scalable, robust, and innovative verification methodologies using cutting‑edge emulation technologies.
Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For.
Job Description:
• Lead Palladium hardware emulation engagements with customers, from initial deployment through advanced use‑case enablement and ongoing optimization
• Serve as the primary technical point of contact for assigned customers, driving successful adoption and long‑term usage of emulation‑based verification flows
• Analyze complex customer verification environments and workflows to identify opportunities for improved scalability, performance, and productivity using hardware‑assisted verification
• Work closely with R&D teams to provide feedback based on real customer use cases, drive enablement and validation of new features and capabilities and include product roadmap
• Develop and maintain high‑quality technical collateral, reference flows, and examples for both customer engagements and internal enablement
• Collaborate with field, support, and R&D teams to reproduce, debug, and resolve complex customer‑reported issues, providing clear technical root‑cause analysis and recommendations
• Act as a technical mentor and subject‑matter expert within the product engineering organization, sharing best practices and lessons learned across engagement
Requirements:
• Complete Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or equivalent practical experience
• 3-5 years of hands‑on experience in RTL verification, with exposure to hardware‑assisted verification (emulation or prototyping)
• Strong fundamentals in digital logic design and RTL development using Verilog/SystemVerilog
• Experience with simulation‑based verification methodologies, testbench development, and debug
• Working knowledge of Linux-based development environments and common EDA workflows
• Proficiency in C/C++ and Python for modeling, automation, and analysis
• Strong analytical, problem-solving, and root-cause analysis skills
• Effective written and verbal communication skills in English, with the ability to collaborate across multiple teams
Nice to Have:
• Course or project work with FPGA based designs and verification
Additional Job Details:
• Employment category: CLT
• Employment term: 40 hours/week.
• Competitive benefits.
• Location: Av Contorno 5800, Belo Horizonte, Minas Gerais Brazil.
Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments.
For more information, access http://www.cadence.com
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Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
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