SoC Top RTL Integration Engineer

Semidynamics is a Barcelona-based semiconductor company, founded in 2016, that designs European processor technology built on the open RISC-V standard. We develop fully customisable 64-bit RISC-V processor IP, including out-of-order and in-order CPU cores and dedicated vector and tensor units, for demanding AI, machine learning and high-performance computing workloads. Our team combines deep architecture expertise with hands-on silicon experience, and we are growing to deliver complete, high-performance SoC solutions to our customers. Role overview We are looking for an SoC Top RTL Integration Engineer to integrate multiple subsystems into the top level of our high-performance SoCs. You will connect CPU clusters, IP blocks and peripherals through interconnects and NoCs, and make sure the integrated design is clean, constrained and ready for tape-out. This is a senior, hands-on role for an engineer who has already integrated large SoCs and taken them to silicon. Key responsibilities • Integrate multiple subsystems (CPU clusters, memory, accelerators, peripherals and third-party IP) into the SoC top-level RTL. • Connect subsystems through interconnects and NoCs using protocols such as AXI, APB and CHI. • Define and integrate the chip's IOs, including connections to pads. • Write and maintain SDC timing constraints for the integrated design, working with physical design teams. • Run, debug and close lint, CDC and RDC checks at SoC top level. • Integrate the top-level clock, reset and power infrastructure, and contribute to UPF power intent. • Develop Python and C scripts and tests to automate integration flows and support bring-up. • Work closely with architecture, verification, DFT and physical design teams to drive the SoC through to tape-out. Required qualifications • Degree in Electrical Engineering, Electronic Engineering, Computer Engineering or a related field. • 8+ years of experience in digital/SoC design. • Strong hands-on RTL design experience (SystemVerilog/Verilog). • Proven experience integrating multiple subsystems on large SoCs. • Experience connecting subsystems through interconnects and/or NoCs, with solid knowledge of AXI and APB. • Proven track record on one or more tape-outs. • Hands-on experience with lint, CDC and RDC checks. • Experience writing and managing SDC constraints and integrating chip IOs. • Working knowledge of Python and C for scripting and automation (user level). • Fluent English, written and spoken. Nice to have • Knowledge of clock, reset and power architectures. • Experience with the CHI coherent interconnect protocol. • Experience with UPF-based low-power design flows and pad ring integration. Why Semidynamics • Work at one of Europe's most promising deep-tech semiconductor scale-ups • Accelerated development path, with room to grow into confidential computing, memory isolation and software security • 4 days per week in the Barcelona office (city center), 1 day working from home • 1 week of work from anywhere in the world • Competitive package • A collaborative, technical, growth-oriented environment that values direct ownership and clear thinking